Merge tag 'drm-vc4-fixes-2016-03-03' of github.com:anholt/linux into drm-next
This pull request fixes the major VC4 HDMI modesetting bugs found when the first wave of users showed up in Raspbian. * tag 'drm-vc4-fixes-2016-03-03' of github.com:anholt/linux: drm/vc4: Initialize scaler DISPBKGND on modeset. drm/vc4: Fix setting of vertical timings in the CRTC. drm/vc4: Fix the name of the VSYNCD_EVEN register. drm/vc4: Add another reg to HDMI debug dumping. drm/vc4: Bring HDMI up from power off if necessary. drm/vc4: Fix a framebuffer reference leak on async flip interrupt.
This commit is contained in:
commit
67d1c0a25c
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@ -88,7 +88,7 @@ static const struct {
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} crtc_regs[] = {
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CRTC_REG(PV_CONTROL),
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CRTC_REG(PV_V_CONTROL),
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CRTC_REG(PV_VSYNCD),
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CRTC_REG(PV_VSYNCD_EVEN),
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CRTC_REG(PV_HORZA),
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CRTC_REG(PV_HORZB),
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CRTC_REG(PV_VERTA),
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@ -188,6 +188,8 @@ static int vc4_get_clock_select(struct drm_crtc *crtc)
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static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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struct vc4_dev *vc4 = to_vc4_dev(dev);
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struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
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struct drm_crtc_state *state = crtc->state;
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struct drm_display_mode *mode = &state->adjusted_mode;
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@ -217,6 +219,16 @@ static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc)
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PV_HORZB_HFP) |
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VC4_SET_FIELD(mode->hdisplay, PV_HORZB_HACTIVE));
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CRTC_WRITE(PV_VERTA,
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VC4_SET_FIELD(mode->vtotal - mode->vsync_end,
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PV_VERTA_VBP) |
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VC4_SET_FIELD(mode->vsync_end - mode->vsync_start,
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PV_VERTA_VSYNC));
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CRTC_WRITE(PV_VERTB,
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VC4_SET_FIELD(mode->vsync_start - mode->vdisplay,
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PV_VERTB_VFP) |
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VC4_SET_FIELD(vactive, PV_VERTB_VACTIVE));
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if (interlace) {
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CRTC_WRITE(PV_VERTA_EVEN,
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VC4_SET_FIELD(mode->vtotal - mode->vsync_end - 1,
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@ -246,6 +258,10 @@ static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc)
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PV_CONTROL_FIFO_CLR |
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PV_CONTROL_EN);
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HVS_WRITE(SCALER_DISPBKGNDX(vc4_crtc->channel),
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SCALER_DISPBKGND_AUTOHS |
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(interlace ? SCALER_DISPBKGND_INTERLACE : 0));
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if (debug_dump_regs) {
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DRM_INFO("CRTC %d regs after:\n", drm_crtc_index(crtc));
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vc4_crtc_dump_regs(vc4_crtc);
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@ -527,6 +543,7 @@ static int vc4_async_page_flip(struct drm_crtc *crtc,
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/* Make sure all other async modesetes have landed. */
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ret = down_interruptible(&vc4->async_modeset);
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if (ret) {
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drm_framebuffer_unreference(fb);
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kfree(flip_state);
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return ret;
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}
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@ -95,6 +95,7 @@ static const struct {
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HDMI_REG(VC4_HDMI_SW_RESET_CONTROL),
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HDMI_REG(VC4_HDMI_HOTPLUG_INT),
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HDMI_REG(VC4_HDMI_HOTPLUG),
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HDMI_REG(VC4_HDMI_RAM_PACKET_CONFIG),
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HDMI_REG(VC4_HDMI_HORZA),
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HDMI_REG(VC4_HDMI_HORZB),
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HDMI_REG(VC4_HDMI_FIFO_CTL),
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@ -495,6 +496,16 @@ static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
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goto err_put_i2c;
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}
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/* This is the rate that is set by the firmware. The number
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* needs to be a bit higher than the pixel clock rate
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* (generally 148.5Mhz).
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*/
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ret = clk_set_rate(hdmi->hsm_clock, 163682864);
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if (ret) {
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DRM_ERROR("Failed to set HSM clock rate: %d\n", ret);
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goto err_unprepare_pix;
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}
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ret = clk_prepare_enable(hdmi->hsm_clock);
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if (ret) {
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DRM_ERROR("Failed to turn on HDMI state machine clock: %d\n",
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@ -516,7 +527,24 @@ static int vc4_hdmi_bind(struct device *dev, struct device *master, void *data)
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vc4->hdmi = hdmi;
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/* HDMI core must be enabled. */
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WARN_ON_ONCE((HD_READ(VC4_HD_M_CTL) & VC4_HD_M_ENABLE) == 0);
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if (!(HD_READ(VC4_HD_M_CTL) & VC4_HD_M_ENABLE)) {
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HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_SW_RST);
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udelay(1);
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HD_WRITE(VC4_HD_M_CTL, 0);
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HD_WRITE(VC4_HD_M_CTL, VC4_HD_M_ENABLE);
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HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL,
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VC4_HDMI_SW_RESET_HDMI |
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VC4_HDMI_SW_RESET_FORMAT_DETECT);
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HDMI_WRITE(VC4_HDMI_SW_RESET_CONTROL, 0);
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/* PHY should be in reset, like
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* vc4_hdmi_encoder_disable() does.
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*/
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HDMI_WRITE(VC4_HDMI_TX_PHY_RESET_CTL, 0xf << 16);
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}
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drm_encoder_init(drm, hdmi->encoder, &vc4_hdmi_encoder_funcs,
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DRM_MODE_ENCODER_TMDS, NULL);
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@ -187,7 +187,7 @@
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# define PV_VCONTROL_CONTINUOUS BIT(1)
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# define PV_VCONTROL_VIDEN BIT(0)
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#define PV_VSYNCD 0x08
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#define PV_VSYNCD_EVEN 0x08
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#define PV_HORZA 0x0c
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# define PV_HORZA_HBP_MASK VC4_MASK(31, 16)
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@ -350,6 +350,17 @@
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# define SCALER_DISPCTRLX_HEIGHT_SHIFT 0
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#define SCALER_DISPBKGND0 0x00000044
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# define SCALER_DISPBKGND_AUTOHS BIT(31)
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# define SCALER_DISPBKGND_INTERLACE BIT(30)
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# define SCALER_DISPBKGND_GAMMA BIT(29)
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# define SCALER_DISPBKGND_TESTMODE_MASK VC4_MASK(28, 25)
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# define SCALER_DISPBKGND_TESTMODE_SHIFT 25
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/* Enables filling the scaler line with the RGB value in the low 24
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* bits before compositing. Costs cycles, so should be skipped if
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* opaque display planes will cover everything.
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*/
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# define SCALER_DISPBKGND_FILL BIT(24)
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#define SCALER_DISPSTAT0 0x00000048
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#define SCALER_DISPBASE0 0x0000004c
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# define SCALER_DISPSTATX_MODE_MASK VC4_MASK(31, 30)
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@ -362,6 +373,9 @@
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# define SCALER_DISPSTATX_EMPTY BIT(28)
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#define SCALER_DISPCTRL1 0x00000050
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#define SCALER_DISPBKGND1 0x00000054
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#define SCALER_DISPBKGNDX(x) (SCALER_DISPBKGND0 + \
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(x) * (SCALER_DISPBKGND1 - \
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SCALER_DISPBKGND0))
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#define SCALER_DISPSTAT1 0x00000058
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#define SCALER_DISPSTATX(x) (SCALER_DISPSTAT0 + \
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(x) * (SCALER_DISPSTAT1 - \
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@ -456,6 +470,8 @@
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#define VC4_HDMI_TX_PHY_RESET_CTL 0x2c0
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#define VC4_HD_M_CTL 0x00c
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# define VC4_HD_M_REGISTER_FILE_STANDBY (3 << 6)
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# define VC4_HD_M_RAM_STANDBY (3 << 4)
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# define VC4_HD_M_SW_RST BIT(2)
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# define VC4_HD_M_ENABLE BIT(0)
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