drm/nv04-nv3x: Implement init-compute-mem.
Init-compute-mem was the last piece missing for nv0x-nv3x card cold-booting. This implementation is somewhat lacking but it's been reported to work on most chipsets it was tested in. Let me know if it breaks suspend to RAM for you. Signed-off-by: Francisco Jerez <currojerez@riseup.net> Tested-by: Patrice Mandin <patmandin@gmail.com> Tested-by: Ben Skeggs <bskeggs@redhat.com> Tested-by: Xavier Chantry <chantry.xavier@gmail.com> Tested-by: Marcin Kościelnicki <koriakin@0x04.net> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>hifive-unleashed-5.1
Francisco Jerez
Ben Skeggs
parent
3c7066bca9
commit
67eda20e6b
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@ -28,6 +28,8 @@
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#include "nouveau_hw.h"
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#include "nouveau_encoder.h"
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#include <linux/io-mapping.h>
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/* these defines are made up */
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#define NV_CIO_CRE_44_HEADA 0x0
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#define NV_CIO_CRE_44_HEADB 0x3
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@ -2067,6 +2069,323 @@ init_zm_index_io(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
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return 5;
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}
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static inline void
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bios_md32(struct nvbios *bios, uint32_t reg,
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uint32_t mask, uint32_t val)
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{
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bios_wr32(bios, reg, (bios_rd32(bios, reg) & ~mask) | val);
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}
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static uint32_t
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peek_fb(struct drm_device *dev, struct io_mapping *fb,
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uint32_t off)
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{
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uint32_t val = 0;
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if (off < pci_resource_len(dev->pdev, 1)) {
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uint32_t __iomem *p = io_mapping_map_atomic_wc(fb, off);
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val = ioread32(p);
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io_mapping_unmap_atomic(p);
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}
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return val;
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}
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static void
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poke_fb(struct drm_device *dev, struct io_mapping *fb,
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uint32_t off, uint32_t val)
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{
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if (off < pci_resource_len(dev->pdev, 1)) {
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uint32_t __iomem *p = io_mapping_map_atomic_wc(fb, off);
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iowrite32(val, p);
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wmb();
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io_mapping_unmap_atomic(p);
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}
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}
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static inline bool
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read_back_fb(struct drm_device *dev, struct io_mapping *fb,
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uint32_t off, uint32_t val)
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{
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poke_fb(dev, fb, off, val);
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return val == peek_fb(dev, fb, off);
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}
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static int
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nv04_init_compute_mem(struct nvbios *bios)
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{
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struct drm_device *dev = bios->dev;
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uint32_t patt = 0xdeadbeef;
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struct io_mapping *fb;
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int i;
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/* Map the framebuffer aperture */
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fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1),
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pci_resource_len(dev->pdev, 1));
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if (!fb)
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return -ENOMEM;
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/* Sequencer and refresh off */
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NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) | 0x20);
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bios_md32(bios, NV04_PFB_DEBUG_0, 0, NV04_PFB_DEBUG_0_REFRESH_OFF);
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bios_md32(bios, NV04_PFB_BOOT_0, ~0,
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NV04_PFB_BOOT_0_RAM_AMOUNT_16MB |
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NV04_PFB_BOOT_0_RAM_WIDTH_128 |
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NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_16MBIT);
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for (i = 0; i < 4; i++)
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poke_fb(dev, fb, 4 * i, patt);
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poke_fb(dev, fb, 0x400000, patt + 1);
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if (peek_fb(dev, fb, 0) == patt + 1) {
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bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_TYPE,
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NV04_PFB_BOOT_0_RAM_TYPE_SDRAM_16MBIT);
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bios_md32(bios, NV04_PFB_DEBUG_0,
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NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
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for (i = 0; i < 4; i++)
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poke_fb(dev, fb, 4 * i, patt);
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if ((peek_fb(dev, fb, 0xc) & 0xffff) != (patt & 0xffff))
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bios_md32(bios, NV04_PFB_BOOT_0,
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NV04_PFB_BOOT_0_RAM_WIDTH_128 |
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NV04_PFB_BOOT_0_RAM_AMOUNT,
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NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
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} else if ((peek_fb(dev, fb, 0xc) & 0xffff0000) !=
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(patt & 0xffff0000)) {
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bios_md32(bios, NV04_PFB_BOOT_0,
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NV04_PFB_BOOT_0_RAM_WIDTH_128 |
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NV04_PFB_BOOT_0_RAM_AMOUNT,
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NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
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} else if (peek_fb(dev, fb, 0) == patt) {
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if (read_back_fb(dev, fb, 0x800000, patt))
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bios_md32(bios, NV04_PFB_BOOT_0,
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NV04_PFB_BOOT_0_RAM_AMOUNT,
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NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
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else
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bios_md32(bios, NV04_PFB_BOOT_0,
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NV04_PFB_BOOT_0_RAM_AMOUNT,
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NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
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bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_TYPE,
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NV04_PFB_BOOT_0_RAM_TYPE_SGRAM_8MBIT);
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} else if (!read_back_fb(dev, fb, 0x800000, patt)) {
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bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
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NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
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}
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/* Refresh on, sequencer on */
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bios_md32(bios, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
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NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) & ~0x20);
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io_mapping_free(fb);
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return 0;
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}
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static const uint8_t *
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nv05_memory_config(struct nvbios *bios)
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{
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/* Defaults for BIOSes lacking a memory config table */
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static const uint8_t default_config_tab[][2] = {
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{ 0x24, 0x00 },
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{ 0x28, 0x00 },
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{ 0x24, 0x01 },
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{ 0x1f, 0x00 },
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{ 0x0f, 0x00 },
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{ 0x17, 0x00 },
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{ 0x06, 0x00 },
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{ 0x00, 0x00 }
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};
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int i = (bios_rd32(bios, NV_PEXTDEV_BOOT_0) &
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NV_PEXTDEV_BOOT_0_RAMCFG) >> 2;
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if (bios->legacy.mem_init_tbl_ptr)
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return &bios->data[bios->legacy.mem_init_tbl_ptr + 2 * i];
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else
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return default_config_tab[i];
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}
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static int
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nv05_init_compute_mem(struct nvbios *bios)
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{
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struct drm_device *dev = bios->dev;
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const uint8_t *ramcfg = nv05_memory_config(bios);
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uint32_t patt = 0xdeadbeef;
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struct io_mapping *fb;
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int i, v;
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/* Map the framebuffer aperture */
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fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1),
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pci_resource_len(dev->pdev, 1));
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if (!fb)
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return -ENOMEM;
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/* Sequencer off */
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NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) | 0x20);
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if (bios_rd32(bios, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_UMA_ENABLE)
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goto out;
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bios_md32(bios, NV04_PFB_DEBUG_0, NV04_PFB_DEBUG_0_REFRESH_OFF, 0);
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/* If present load the hardcoded scrambling table */
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if (bios->legacy.mem_init_tbl_ptr) {
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uint32_t *scramble_tab = (uint32_t *)&bios->data[
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bios->legacy.mem_init_tbl_ptr + 0x10];
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for (i = 0; i < 8; i++)
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bios_wr32(bios, NV04_PFB_SCRAMBLE(i),
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ROM32(scramble_tab[i]));
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}
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/* Set memory type/width/length defaults depending on the straps */
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bios_md32(bios, NV04_PFB_BOOT_0, 0x3f, ramcfg[0]);
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if (ramcfg[1] & 0x80)
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bios_md32(bios, NV04_PFB_CFG0, 0, NV04_PFB_CFG0_SCRAMBLE);
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bios_md32(bios, NV04_PFB_CFG1, 0x700001, (ramcfg[1] & 1) << 20);
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bios_md32(bios, NV04_PFB_CFG1, 0, 1);
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/* Probe memory bus width */
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for (i = 0; i < 4; i++)
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poke_fb(dev, fb, 4 * i, patt);
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if (peek_fb(dev, fb, 0xc) != patt)
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bios_md32(bios, NV04_PFB_BOOT_0,
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NV04_PFB_BOOT_0_RAM_WIDTH_128, 0);
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/* Probe memory length */
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v = bios_rd32(bios, NV04_PFB_BOOT_0) & NV04_PFB_BOOT_0_RAM_AMOUNT;
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if (v == NV04_PFB_BOOT_0_RAM_AMOUNT_32MB &&
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(!read_back_fb(dev, fb, 0x1000000, ++patt) ||
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!read_back_fb(dev, fb, 0, ++patt)))
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bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
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NV04_PFB_BOOT_0_RAM_AMOUNT_16MB);
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if (v == NV04_PFB_BOOT_0_RAM_AMOUNT_16MB &&
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!read_back_fb(dev, fb, 0x800000, ++patt))
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bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
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NV04_PFB_BOOT_0_RAM_AMOUNT_8MB);
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if (!read_back_fb(dev, fb, 0x400000, ++patt))
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bios_md32(bios, NV04_PFB_BOOT_0, NV04_PFB_BOOT_0_RAM_AMOUNT,
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NV04_PFB_BOOT_0_RAM_AMOUNT_4MB);
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out:
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/* Sequencer on */
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NVWriteVgaSeq(dev, 0, 1, NVReadVgaSeq(dev, 0, 1) & ~0x20);
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io_mapping_free(fb);
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return 0;
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}
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static int
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nv10_init_compute_mem(struct nvbios *bios)
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{
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struct drm_device *dev = bios->dev;
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struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
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const int mem_width[] = { 0x10, 0x00, 0x20 };
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const int mem_width_count = (dev_priv->chipset >= 0x17 ? 3 : 2);
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uint32_t patt = 0xdeadbeef;
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struct io_mapping *fb;
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int i, j, k;
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/* Map the framebuffer aperture */
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fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1),
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pci_resource_len(dev->pdev, 1));
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if (!fb)
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return -ENOMEM;
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bios_wr32(bios, NV10_PFB_REFCTRL, NV10_PFB_REFCTRL_VALID_1);
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/* Probe memory bus width */
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for (i = 0; i < mem_width_count; i++) {
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bios_md32(bios, NV04_PFB_CFG0, 0x30, mem_width[i]);
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for (j = 0; j < 4; j++) {
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for (k = 0; k < 4; k++)
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poke_fb(dev, fb, 0x1c, 0);
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poke_fb(dev, fb, 0x1c, patt);
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poke_fb(dev, fb, 0x3c, 0);
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if (peek_fb(dev, fb, 0x1c) == patt)
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goto mem_width_found;
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}
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}
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mem_width_found:
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patt <<= 1;
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/* Probe amount of installed memory */
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for (i = 0; i < 4; i++) {
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int off = bios_rd32(bios, NV04_PFB_FIFO_DATA) - 0x100000;
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poke_fb(dev, fb, off, patt);
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poke_fb(dev, fb, 0, 0);
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peek_fb(dev, fb, 0);
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peek_fb(dev, fb, 0);
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peek_fb(dev, fb, 0);
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peek_fb(dev, fb, 0);
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if (peek_fb(dev, fb, off) == patt)
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goto amount_found;
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}
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/* IC missing - disable the upper half memory space. */
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bios_md32(bios, NV04_PFB_CFG0, 0x1000, 0);
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amount_found:
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io_mapping_free(fb);
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return 0;
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}
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static int
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nv20_init_compute_mem(struct nvbios *bios)
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{
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struct drm_device *dev = bios->dev;
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struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
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uint32_t mask = (dev_priv->chipset >= 0x25 ? 0x300 : 0x900);
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uint32_t amount, off;
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struct io_mapping *fb;
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/* Map the framebuffer aperture */
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fb = io_mapping_create_wc(pci_resource_start(dev->pdev, 1),
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pci_resource_len(dev->pdev, 1));
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if (!fb)
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return -ENOMEM;
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bios_wr32(bios, NV10_PFB_REFCTRL, NV10_PFB_REFCTRL_VALID_1);
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/* Allow full addressing */
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bios_md32(bios, NV04_PFB_CFG0, 0, mask);
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amount = bios_rd32(bios, NV04_PFB_FIFO_DATA);
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for (off = amount; off > 0x2000000; off -= 0x2000000)
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poke_fb(dev, fb, off - 4, off);
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amount = bios_rd32(bios, NV04_PFB_FIFO_DATA);
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if (amount != peek_fb(dev, fb, amount - 4))
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/* IC missing - disable the upper half memory space. */
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bios_md32(bios, NV04_PFB_CFG0, mask, 0);
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io_mapping_free(fb);
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return 0;
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}
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static int
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init_compute_mem(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
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{
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@ -2075,64 +2394,57 @@ init_compute_mem(struct nvbios *bios, uint16_t offset, struct init_exec *iexec)
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*
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* offset (8 bit): opcode
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*
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* This opcode is meant to set NV_PFB_CFG0 (0x100200) appropriately so
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* that the hardware can correctly calculate how much VRAM it has
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* (and subsequently report that value in NV_PFB_CSTATUS (0x10020C))
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* This opcode is meant to set the PFB memory config registers
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* appropriately so that we can correctly calculate how much VRAM it
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* has (on nv10 and better chipsets the amount of installed VRAM is
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* subsequently reported in NV_PFB_CSTATUS (0x10020C)).
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*
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* The implementation of this opcode in general consists of two parts:
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* 1) determination of the memory bus width
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* 2) determination of how many of the card's RAM pads have ICs attached
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* The implementation of this opcode in general consists of several
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* parts:
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*
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* 1) is done by a cunning combination of writes to offsets 0x1c and
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* 0x3c in the framebuffer, and seeing whether the written values are
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* read back correctly. This then affects bits 4-7 of NV_PFB_CFG0
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* 1) Determination of memory type and density. Only necessary for
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* really old chipsets, the memory type reported by the strap bits
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* (0x101000) is assumed to be accurate on nv05 and newer.
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*
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* 2) is done by a cunning combination of writes to an offset slightly
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* less than the maximum memory reported by NV_PFB_CSTATUS, then seeing
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* if the test pattern can be read back. This then affects bits 12-15 of
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* NV_PFB_CFG0
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* 2) Determination of the memory bus width. Usually done by a cunning
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* combination of writes to offsets 0x1c and 0x3c in the fb, and
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* seeing whether the written values are read back correctly.
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*
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* In this context a "cunning combination" may include multiple reads
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* and writes to varying locations, often alternating the test pattern
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* and 0, doubtless to make sure buffers are filled, residual charges
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* on tracks are removed etc.
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* Only necessary on nv0x-nv1x and nv34, on the other cards we can
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* trust the straps.
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*
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* Unfortunately, the "cunning combination"s mentioned above, and the
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* changes to the bits in NV_PFB_CFG0 differ with nearly every bios
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* trace I have.
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* 3) Determination of how many of the card's RAM pads have ICs
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* attached, usually done by a cunning combination of writes to an
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* offset slightly less than the maximum memory reported by
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* NV_PFB_CSTATUS, then seeing if the test pattern can be read back.
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*
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* Therefore, we cheat and assume the value of NV_PFB_CFG0 with which
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* we started was correct, and use that instead
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* This appears to be a NOP on IGPs and NV4x or newer chipsets, both io
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* logs of the VBIOS and kmmio traces of the binary driver POSTing the
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* card show nothing being done for this opcode. Why is it still listed
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* in the table?!
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*/
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/* no iexec->execute check by design */
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/*
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* This appears to be a NOP on G8x chipsets, both io logs of the VBIOS
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* and kmmio traces of the binary driver POSTing the card show nothing
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* being done for this opcode. why is it still listed in the table?!
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*/
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struct drm_nouveau_private *dev_priv = bios->dev->dev_private;
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int ret;
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if (dev_priv->card_type >= NV_40)
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return 1;
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if (dev_priv->chipset >= 0x40 ||
|
||||
dev_priv->chipset == 0x1a ||
|
||||
dev_priv->chipset == 0x1f)
|
||||
ret = 0;
|
||||
else if (dev_priv->chipset >= 0x20 &&
|
||||
dev_priv->chipset != 0x34)
|
||||
ret = nv20_init_compute_mem(bios);
|
||||
else if (dev_priv->chipset >= 0x10)
|
||||
ret = nv10_init_compute_mem(bios);
|
||||
else if (dev_priv->chipset >= 0x5)
|
||||
ret = nv05_init_compute_mem(bios);
|
||||
else
|
||||
ret = nv04_init_compute_mem(bios);
|
||||
|
||||
/*
|
||||
* On every card I've seen, this step gets done for us earlier in
|
||||
* the init scripts
|
||||
uint8_t crdata = bios_idxprt_rd(dev, NV_VIO_SRX, 0x01);
|
||||
bios_idxprt_wr(dev, NV_VIO_SRX, 0x01, crdata | 0x20);
|
||||
*/
|
||||
|
||||
/*
|
||||
* This also has probably been done in the scripts, but an mmio trace of
|
||||
* s3 resume shows nvidia doing it anyway (unlike the NV_VIO_SRX write)
|
||||
*/
|
||||
bios_wr32(bios, NV10_PFB_REFCTRL, NV10_PFB_REFCTRL_VALID_1);
|
||||
|
||||
/* write back the saved configuration value */
|
||||
bios_wr32(bios, NV04_PFB_CFG0, bios->state.saved_nv_pfb_cfg0);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
|
@ -6320,7 +6632,6 @@ nouveau_bios_init(struct drm_device *dev)
|
|||
{
|
||||
struct drm_nouveau_private *dev_priv = dev->dev_private;
|
||||
struct nvbios *bios = &dev_priv->vbios;
|
||||
uint32_t saved_nv_pextdev_boot_0;
|
||||
bool was_locked;
|
||||
int ret;
|
||||
|
||||
|
|
@ -6341,27 +6652,16 @@ nouveau_bios_init(struct drm_device *dev)
|
|||
if (!bios->major_version) /* we don't run version 0 bios */
|
||||
return 0;
|
||||
|
||||
/* these will need remembering across a suspend */
|
||||
saved_nv_pextdev_boot_0 = bios_rd32(bios, NV_PEXTDEV_BOOT_0);
|
||||
bios->state.saved_nv_pfb_cfg0 = bios_rd32(bios, NV04_PFB_CFG0);
|
||||
|
||||
/* init script execution disabled */
|
||||
bios->execute = false;
|
||||
|
||||
/* ... unless card isn't POSTed already */
|
||||
if (!nouveau_bios_posted(dev)) {
|
||||
NV_INFO(dev, "Adaptor not initialised\n");
|
||||
if (dev_priv->card_type < NV_40) {
|
||||
NV_ERROR(dev, "Unable to POST this chipset\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
NV_INFO(dev, "Running VBIOS init tables\n");
|
||||
NV_INFO(dev, "Adaptor not initialised, "
|
||||
"running VBIOS init tables.\n");
|
||||
bios->execute = true;
|
||||
}
|
||||
|
||||
bios_wr32(bios, NV_PEXTDEV_BOOT_0, saved_nv_pextdev_boot_0);
|
||||
|
||||
ret = nouveau_run_vbios_init(dev);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
|
|
|||
|
|
@ -251,8 +251,6 @@ struct nvbios {
|
|||
|
||||
struct {
|
||||
int crtchead;
|
||||
/* these need remembering across suspend */
|
||||
uint32_t saved_nv_pfb_cfg0;
|
||||
} state;
|
||||
|
||||
struct {
|
||||
|
|
|
|||
Loading…
Reference in New Issue