drm/vc4: Fix support for interlaced modes on HDMI.
We really do need to be using the halved V fields. I had been confused by the code I was using as a reference because it stored halved vsync fields but not halved vdisplay, so it looked like I only needed to divide vdisplay by 2. This reverts part of Mario's timestamping fixes that prevented CRTC_HALVE_V from applying, and instead adjusts the timestamping code to not use the crtc field in that case. Fixes locking of 1920x1080x60i on my Dell 2408WFP. There are black bars on the top and bottom, but I suspect that might be an under/overscan flags problem as opposed to video timings. Signed-off-by: Eric Anholt <eric@anholt.net>
This commit is contained in:
Eric Anholt
parent
2b29bf1661
commit
682e62c454
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@ -229,7 +229,7 @@ int vc4_crtc_get_scanoutpos(struct drm_device *dev, unsigned int crtc_id,
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* and need to make things up in a approximative but consistent way.
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*/
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ret |= DRM_SCANOUTPOS_IN_VBLANK;
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vblank_lines = mode->crtc_vtotal - mode->crtc_vdisplay;
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vblank_lines = mode->vtotal - mode->vdisplay;
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if (flags & DRM_CALLED_FROM_VBLIRQ) {
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/*
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@ -378,7 +378,6 @@ static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc)
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struct drm_crtc_state *state = crtc->state;
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struct drm_display_mode *mode = &state->adjusted_mode;
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bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
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u32 vactive = (mode->vdisplay >> (interlace ? 1 : 0));
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u32 format = PV_CONTROL_FORMAT_24;
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bool debug_dump_regs = false;
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int clock_select = vc4_get_clock_select(crtc);
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@ -404,32 +403,46 @@ static void vc4_crtc_mode_set_nofb(struct drm_crtc *crtc)
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VC4_SET_FIELD(mode->hdisplay, PV_HORZB_HACTIVE));
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CRTC_WRITE(PV_VERTA,
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VC4_SET_FIELD(mode->vtotal - mode->vsync_end,
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VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
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PV_VERTA_VBP) |
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VC4_SET_FIELD(mode->vsync_end - mode->vsync_start,
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VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
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PV_VERTA_VSYNC));
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CRTC_WRITE(PV_VERTB,
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VC4_SET_FIELD(mode->vsync_start - mode->vdisplay,
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VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
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PV_VERTB_VFP) |
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VC4_SET_FIELD(vactive, PV_VERTB_VACTIVE));
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VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
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if (interlace) {
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CRTC_WRITE(PV_VERTA_EVEN,
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VC4_SET_FIELD(mode->vtotal - mode->vsync_end - 1,
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VC4_SET_FIELD(mode->crtc_vtotal -
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mode->crtc_vsync_end - 1,
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PV_VERTA_VBP) |
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VC4_SET_FIELD(mode->vsync_end - mode->vsync_start,
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VC4_SET_FIELD(mode->crtc_vsync_end -
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mode->crtc_vsync_start,
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PV_VERTA_VSYNC));
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CRTC_WRITE(PV_VERTB_EVEN,
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VC4_SET_FIELD(mode->vsync_start - mode->vdisplay,
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VC4_SET_FIELD(mode->crtc_vsync_start -
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mode->crtc_vdisplay,
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PV_VERTB_VFP) |
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VC4_SET_FIELD(vactive, PV_VERTB_VACTIVE));
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VC4_SET_FIELD(mode->crtc_vdisplay, PV_VERTB_VACTIVE));
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/* We set up first field even mode for HDMI. VEC's
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* NTSC mode would want first field odd instead, once
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* we support it (to do so, set ODD_FIRST and put the
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* delay in VSYNCD_EVEN instead).
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*/
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CRTC_WRITE(PV_V_CONTROL,
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PV_VCONTROL_CONTINUOUS |
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PV_VCONTROL_INTERLACE |
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VC4_SET_FIELD(mode->htotal / 2,
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PV_VCONTROL_ODD_DELAY));
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CRTC_WRITE(PV_VSYNCD_EVEN, 0);
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} else {
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CRTC_WRITE(PV_V_CONTROL, PV_VCONTROL_CONTINUOUS);
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}
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CRTC_WRITE(PV_HACT_ACT, mode->hdisplay);
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CRTC_WRITE(PV_V_CONTROL,
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PV_VCONTROL_CONTINUOUS |
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(interlace ? PV_VCONTROL_INTERLACE : 0));
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CRTC_WRITE(PV_CONTROL,
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VC4_SET_FIELD(format, PV_CONTROL_FORMAT) |
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@ -544,16 +557,6 @@ static bool vc4_crtc_mode_fixup(struct drm_crtc *crtc,
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return false;
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}
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/*
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* Interlaced video modes got CRTC_INTERLACE_HALVE_V applied when
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* coming from user space. We don't want this, as it screws up
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* vblank timestamping, so fix it up.
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*/
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drm_mode_set_crtcinfo(adjusted_mode, 0);
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DRM_DEBUG_KMS("[CRTC:%d] adjusted_mode :\n", crtc->base.id);
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drm_mode_debug_printmodeline(adjusted_mode);
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return true;
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}
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@ -211,35 +211,10 @@ static int vc4_hdmi_connector_get_modes(struct drm_connector *connector)
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return ret;
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}
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/*
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* drm_helper_probe_single_connector_modes() applies drm_mode_set_crtcinfo to
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* all modes with flag CRTC_INTERLACE_HALVE_V. We don't want this, as it
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* screws up vblank timestamping for interlaced modes, so fix it up.
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*/
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static int vc4_hdmi_connector_probe_modes(struct drm_connector *connector,
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uint32_t maxX, uint32_t maxY)
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{
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struct drm_display_mode *mode;
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int count;
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count = drm_helper_probe_single_connector_modes(connector, maxX, maxY);
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if (count == 0)
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return 0;
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DRM_DEBUG_KMS("[CONNECTOR:%d:%s] probed adapted modes :\n",
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connector->base.id, connector->name);
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list_for_each_entry(mode, &connector->modes, head) {
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drm_mode_set_crtcinfo(mode, 0);
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drm_mode_debug_printmodeline(mode);
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}
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return count;
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}
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static const struct drm_connector_funcs vc4_hdmi_connector_funcs = {
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.dpms = drm_atomic_helper_connector_dpms,
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.detect = vc4_hdmi_connector_detect,
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.fill_modes = vc4_hdmi_connector_probe_modes,
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.fill_modes = drm_helper_probe_single_connector_modes,
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.destroy = vc4_hdmi_connector_destroy,
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.reset = drm_atomic_helper_connector_reset,
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.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
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@ -307,16 +282,20 @@ static void vc4_hdmi_encoder_mode_set(struct drm_encoder *encoder,
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bool debug_dump_regs = false;
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bool hsync_pos = mode->flags & DRM_MODE_FLAG_PHSYNC;
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bool vsync_pos = mode->flags & DRM_MODE_FLAG_PVSYNC;
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u32 vactive = (mode->vdisplay >>
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((mode->flags & DRM_MODE_FLAG_INTERLACE) ? 1 : 0));
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u32 verta = (VC4_SET_FIELD(mode->vsync_end - mode->vsync_start,
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bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
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u32 verta = (VC4_SET_FIELD(mode->crtc_vsync_end - mode->crtc_vsync_start,
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VC4_HDMI_VERTA_VSP) |
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VC4_SET_FIELD(mode->vsync_start - mode->vdisplay,
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VC4_SET_FIELD(mode->crtc_vsync_start - mode->crtc_vdisplay,
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VC4_HDMI_VERTA_VFP) |
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VC4_SET_FIELD(vactive, VC4_HDMI_VERTA_VAL));
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VC4_SET_FIELD(mode->crtc_vdisplay, VC4_HDMI_VERTA_VAL));
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u32 vertb = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
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VC4_SET_FIELD(mode->vtotal - mode->vsync_end,
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VC4_SET_FIELD(mode->crtc_vtotal - mode->crtc_vsync_end,
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VC4_HDMI_VERTB_VBP));
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u32 vertb_even = (VC4_SET_FIELD(0, VC4_HDMI_VERTB_VSPO) |
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VC4_SET_FIELD(mode->crtc_vtotal -
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mode->crtc_vsync_end -
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interlaced,
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VC4_HDMI_VERTB_VBP));
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u32 csc_ctl;
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if (debug_dump_regs) {
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@ -349,7 +328,7 @@ static void vc4_hdmi_encoder_mode_set(struct drm_encoder *encoder,
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HDMI_WRITE(VC4_HDMI_VERTA0, verta);
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HDMI_WRITE(VC4_HDMI_VERTA1, verta);
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HDMI_WRITE(VC4_HDMI_VERTB0, vertb);
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HDMI_WRITE(VC4_HDMI_VERTB0, vertb_even);
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HDMI_WRITE(VC4_HDMI_VERTB1, vertb);
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HD_WRITE(VC4_HD_VID_CTL,
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@ -183,6 +183,9 @@
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# define PV_CONTROL_EN BIT(0)
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#define PV_V_CONTROL 0x04
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# define PV_VCONTROL_ODD_DELAY_MASK VC4_MASK(22, 6)
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# define PV_VCONTROL_ODD_DELAY_SHIFT 6
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# define PV_VCONTROL_ODD_FIRST BIT(5)
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# define PV_VCONTROL_INTERLACE BIT(4)
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# define PV_VCONTROL_CONTINUOUS BIT(1)
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# define PV_VCONTROL_VIDEN BIT(0)
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