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MIPS: Correct MIPS16 BREAK code interpretation 

Correct the interpretation of the immediate MIPS16 BREAK instruction
code embedded in the instruction word across bits 10:5 rather than 11:6
as current code implies, fixing the interpretation of integer overflow
and divide by zero traps.

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9695/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
hifive-unleashed-5.1
Maciej W. Rozycki 2015-04-03 23:26:21 +01:00 committed by Ralf Baechle
parent 18a2c2c6b9
commit 68893e0051
1 changed files with 1 additions and 1 deletions
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2
arch/mips/kernel/traps.c
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@ -925,7 +925,7 @@ asmlinkage void do_bp(struct pt_regs *regs)
if (__get_user(instr[0],
(u16 __user *)msk_isa16_mode(epc)))
goto out_sigsegv;
bcode = (instr[0] >> 6) & 0x3f;
bcode = (instr[0] >> 5) & 0x3f;
do_trap_or_bp(regs, bcode, "Break");
goto out;
}