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soundwire: cadence_master: simplify bus clash interrupt clear 

The bus clash interrupts are generated when the status is one, and
also cleared by writing a one. It's overkill/useless to use an OR when
the bit is already set.

Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Link: https://lore.kernel.org/r/20190725234032.21152-12-pierre-louis.bossart@linux.intel.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
alistair/sunxi64-5.4-dsi
Pierre-Louis Bossart 2019-07-25 18:40:03 -05:00 committed by Vinod Koul
parent 0fc6041d7a
commit 68acd85996
1 changed files with 0 additions and 2 deletions
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2
drivers/soundwire/cadence_master.c
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@ -578,7 +578,6 @@ irqreturn_t sdw_cdns_irq(int irq, void *dev_id)
if (int_status & CDNS_MCP_INT_CTRL_CLASH) {
/* Slave is driving bit slot during control word */
dev_err_ratelimited(cdns->dev, "Bus clash for control word\n");
int_status |= CDNS_MCP_INT_CTRL_CLASH;
}
if (int_status & CDNS_MCP_INT_DATA_CLASH) {
@ -587,7 +586,6 @@ irqreturn_t sdw_cdns_irq(int irq, void *dev_id)
* ownership of data bits or Slave gone bonkers
*/
dev_err_ratelimited(cdns->dev, "Bus clash for data word\n");
int_status |= CDNS_MCP_INT_DATA_CLASH;
}
if (int_status & CDNS_MCP_INT_SLAVE_MASK) {