ARM: sunxi: dt: Reorganize the dtsi
In the early days, the A10 and A13 shared quite some code. Nowadays it shares less and less code, the A31 diverging even more, so it doesn't make much sense to continue to maintain this structure, just use one DTSI for every SoC, and that's it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>hifive-unleashed-5.1
Maxime Ripard
parent
36386d6e54
commit
69144e3baf
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@ -26,7 +26,7 @@
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bootargs = "earlyprintk console=ttyS0,115200";
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};
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soc {
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soc@01c20000 {
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pinctrl@01c20800 {
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led_pins_cubieboard: led_pins@0 {
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allwinner,pins = "PH20", "PH21";
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@ -22,7 +22,7 @@
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bootargs = "earlyprintk console=ttyS0,115200";
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};
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soc {
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soc@01c20000 {
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uart0: serial@01c28000 {
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pinctrl-names = "default";
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pinctrl-0 = <&uart0_pins_a>;
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@ -10,14 +10,172 @@
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* http://www.gnu.org/copyleft/gpl.html
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*/
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/include/ "sunxi.dtsi"
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/include/ "skeleton.dtsi"
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/ {
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interrupt-parent = <&intc>;
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cpus {
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cpu@0 {
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compatible = "arm,cortex-a8";
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};
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};
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memory {
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reg = <0x40000000 0x80000000>;
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};
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soc {
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clocks {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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/*
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* This is a dummy clock, to be used as placeholder on
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* other mux clocks when a specific parent clock is not
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* yet implemented. It should be dropped when the driver
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* is complete.
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*/
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dummy: dummy {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <0>;
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};
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osc24M_fixed: osc24M_fixed {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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};
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osc24M: osc24M@01c20050 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-osc-clk";
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reg = <0x01c20050 0x4>;
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clocks = <&osc24M_fixed>;
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};
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osc32k: osc32k {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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};
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pll1: pll1@01c20000 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-pll1-clk";
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reg = <0x01c20000 0x4>;
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clocks = <&osc24M>;
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};
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/* dummy is 200M */
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cpu: cpu@01c20054 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-cpu-clk";
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reg = <0x01c20054 0x4>;
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clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
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};
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axi: axi@01c20054 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-axi-clk";
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reg = <0x01c20054 0x4>;
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clocks = <&cpu>;
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};
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axi_gates: axi_gates@01c2005c {
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-axi-gates-clk";
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reg = <0x01c2005c 0x4>;
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clocks = <&axi>;
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clock-output-names = "axi_dram";
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};
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ahb: ahb@01c20054 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-ahb-clk";
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reg = <0x01c20054 0x4>;
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clocks = <&axi>;
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};
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ahb_gates: ahb_gates@01c20060 {
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-ahb-gates-clk";
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reg = <0x01c20060 0x8>;
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clocks = <&ahb>;
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clock-output-names = "ahb_usb0", "ahb_ehci0",
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"ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
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"ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
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"ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
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"ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts",
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"ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
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"ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
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"ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
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"ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
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"ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
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"ahb_de_fe1", "ahb_mp", "ahb_mali400";
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};
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apb0: apb0@01c20054 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-apb0-clk";
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reg = <0x01c20054 0x4>;
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clocks = <&ahb>;
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};
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apb0_gates: apb0_gates@01c20068 {
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-apb0-gates-clk";
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reg = <0x01c20068 0x4>;
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clocks = <&apb0>;
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clock-output-names = "apb0_codec", "apb0_spdif",
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"apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
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"apb0_ir1", "apb0_keypad";
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};
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/* dummy is pll62 */
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apb1_mux: apb1_mux@01c20058 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-apb1-mux-clk";
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reg = <0x01c20058 0x4>;
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clocks = <&osc24M>, <&dummy>, <&osc32k>;
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};
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apb1: apb1@01c20058 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-apb1-clk";
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reg = <0x01c20058 0x4>;
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clocks = <&apb1_mux>;
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};
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apb1_gates: apb1_gates@01c2006c {
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-apb1-gates-clk";
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reg = <0x01c2006c 0x4>;
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clocks = <&apb1>;
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clock-output-names = "apb1_i2c0", "apb1_i2c1",
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"apb1_i2c2", "apb1_can", "apb1_scr",
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"apb1_ps20", "apb1_ps21", "apb1_uart0",
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"apb1_uart1", "apb1_uart2", "apb1_uart3",
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"apb1_uart4", "apb1_uart5", "apb1_uart6",
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"apb1_uart7";
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};
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};
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soc@01c20000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x01c20000 0x300000>;
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ranges;
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intc: interrupt-controller@01c20400 {
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compatible = "allwinner,sunxi-ic";
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reg = <0x01c20400 0x400>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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pio: pinctrl@01c20800 {
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compatible = "allwinner,sun4i-a10-pinctrl";
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reg = <0x01c20800 0x400>;
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@ -49,6 +207,18 @@
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};
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};
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timer@01c20c00 {
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compatible = "allwinner,sunxi-timer";
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reg = <0x01c20c00 0x90>;
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interrupts = <22>;
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clocks = <&osc24M>;
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};
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wdt: watchdog@01c20c90 {
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compatible = "allwinner,sunxi-wdt";
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reg = <0x01c20c90 0x10>;
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};
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uart0: serial@01c28000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c28000 0x400>;
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@ -59,6 +229,16 @@
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status = "disabled";
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};
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uart1: serial@01c28400 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c28400 0x400>;
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interrupts = <2>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&apb1_gates 17>;
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status = "disabled";
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};
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uart2: serial@01c28800 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c28800 0x400>;
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@ -69,6 +249,16 @@
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status = "disabled";
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};
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uart3: serial@01c28c00 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c28c00 0x400>;
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interrupts = <4>;
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reg-shift = <2>;
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reg-io-width = <4>;
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clocks = <&apb1_gates 19>;
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status = "disabled";
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};
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uart4: serial@01c29000 {
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compatible = "snps,dw-apb-uart";
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reg = <0x01c29000 0x400>;
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@ -22,7 +22,7 @@
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bootargs = "earlyprintk console=ttyS0,115200";
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};
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soc {
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soc@01c20000 {
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pinctrl@01c20800 {
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led_pins_olinuxino: led_pins@0 {
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allwinner,pins = "PG9";
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@ -11,14 +11,172 @@
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* http://www.gnu.org/copyleft/gpl.html
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*/
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/include/ "sunxi.dtsi"
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/include/ "skeleton.dtsi"
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/ {
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interrupt-parent = <&intc>;
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cpus {
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cpu@0 {
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compatible = "arm,cortex-a8";
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};
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};
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memory {
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reg = <0x40000000 0x20000000>;
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};
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soc {
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clocks {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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/*
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* This is a dummy clock, to be used as placeholder on
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* other mux clocks when a specific parent clock is not
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* yet implemented. It should be dropped when the driver
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* is complete.
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*/
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dummy: dummy {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <0>;
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};
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osc24M_fixed: osc24M_fixed {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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};
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osc24M: osc24M@01c20050 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-osc-clk";
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reg = <0x01c20050 0x4>;
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clocks = <&osc24M_fixed>;
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};
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osc32k: osc32k {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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};
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pll1: pll1@01c20000 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-pll1-clk";
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reg = <0x01c20000 0x4>;
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clocks = <&osc24M>;
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};
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/* dummy is 200M */
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cpu: cpu@01c20054 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-cpu-clk";
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reg = <0x01c20054 0x4>;
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clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
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};
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axi: axi@01c20054 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-axi-clk";
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reg = <0x01c20054 0x4>;
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clocks = <&cpu>;
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};
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axi_gates: axi_gates@01c2005c {
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-axi-gates-clk";
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reg = <0x01c2005c 0x4>;
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clocks = <&axi>;
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clock-output-names = "axi_dram";
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};
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ahb: ahb@01c20054 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-ahb-clk";
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reg = <0x01c20054 0x4>;
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clocks = <&axi>;
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};
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ahb_gates: ahb_gates@01c20060 {
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-ahb-gates-clk";
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reg = <0x01c20060 0x8>;
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clocks = <&ahb>;
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clock-output-names = "ahb_usb0", "ahb_ehci0",
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"ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
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"ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
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"ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
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"ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts",
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"ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
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"ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
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"ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
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"ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
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"ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
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"ahb_de_fe1", "ahb_mp", "ahb_mali400";
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};
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apb0: apb0@01c20054 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-apb0-clk";
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reg = <0x01c20054 0x4>;
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clocks = <&ahb>;
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};
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apb0_gates: apb0_gates@01c20068 {
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-apb0-gates-clk";
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reg = <0x01c20068 0x4>;
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clocks = <&apb0>;
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clock-output-names = "apb0_codec", "apb0_spdif",
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"apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
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"apb0_ir1", "apb0_keypad";
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};
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/* dummy is pll62 */
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apb1_mux: apb1_mux@01c20058 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-apb1-mux-clk";
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reg = <0x01c20058 0x4>;
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clocks = <&osc24M>, <&dummy>, <&osc32k>;
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};
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apb1: apb1@01c20058 {
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#clock-cells = <0>;
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compatible = "allwinner,sun4i-apb1-clk";
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reg = <0x01c20058 0x4>;
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clocks = <&apb1_mux>;
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};
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apb1_gates: apb1_gates@01c2006c {
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#clock-cells = <1>;
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compatible = "allwinner,sun4i-apb1-gates-clk";
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reg = <0x01c2006c 0x4>;
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clocks = <&apb1>;
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clock-output-names = "apb1_i2c0", "apb1_i2c1",
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"apb1_i2c2", "apb1_can", "apb1_scr",
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"apb1_ps20", "apb1_ps21", "apb1_uart0",
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"apb1_uart1", "apb1_uart2", "apb1_uart3",
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"apb1_uart4", "apb1_uart5", "apb1_uart6",
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"apb1_uart7";
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};
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};
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soc@01c20000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x01c20000 0x300000>;
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ranges;
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intc: interrupt-controller@01c20400 {
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compatible = "allwinner,sunxi-ic";
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reg = <0x01c20400 0x400>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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pio: pinctrl@01c20800 {
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compatible = "allwinner,sun5i-a13-pinctrl";
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reg = <0x01c20800 0x400>;
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@ -42,5 +200,37 @@
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allwinner,pull = <0>;
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};
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};
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timer@01c20c00 {
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compatible = "allwinner,sunxi-timer";
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reg = <0x01c20c00 0x90>;
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interrupts = <22>;
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clocks = <&osc24M>;
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};
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|
||||
wdt: watchdog@01c20c90 {
|
||||
compatible = "allwinner,sunxi-wdt";
|
||||
reg = <0x01c20c90 0x10>;
|
||||
};
|
||||
|
||||
uart1: serial@01c28400 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x01c28400 0x400>;
|
||||
interrupts = <2>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&apb1_gates 17>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@01c28c00 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x01c28c00 0x400>;
|
||||
interrupts = <4>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&apb1_gates 19>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
|
|
|||
|
|
@ -1,208 +0,0 @@
|
|||
/*
|
||||
* Copyright 2012 Maxime Ripard
|
||||
*
|
||||
* Maxime Ripard <maxime.ripard@free-electrons.com>
|
||||
*
|
||||
* The code contained herein is licensed under the GNU General Public
|
||||
* License. You may obtain a copy of the GNU General Public License
|
||||
* Version 2 or later at the following locations:
|
||||
*
|
||||
* http://www.opensource.org/licenses/gpl-license.html
|
||||
* http://www.gnu.org/copyleft/gpl.html
|
||||
*/
|
||||
|
||||
/include/ "skeleton.dtsi"
|
||||
|
||||
/ {
|
||||
interrupt-parent = <&intc>;
|
||||
|
||||
cpus {
|
||||
cpu@0 {
|
||||
compatible = "arm,cortex-a8";
|
||||
};
|
||||
};
|
||||
|
||||
clocks {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
|
||||
/*
|
||||
* This is a dummy clock, to be used as placeholder on
|
||||
* other mux clocks when a specific parent clock is not
|
||||
* yet implemented. It should be dropped when the driver
|
||||
* is complete.
|
||||
*/
|
||||
dummy: dummy {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
osc24M_fixed: osc24M_fixed {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <24000000>;
|
||||
};
|
||||
|
||||
osc24M: osc24M@01c20050 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-osc-clk";
|
||||
reg = <0x01c20050 0x4>;
|
||||
clocks = <&osc24M_fixed>;
|
||||
};
|
||||
|
||||
osc32k: osc32k {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
pll1: pll1@01c20000 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-pll1-clk";
|
||||
reg = <0x01c20000 0x4>;
|
||||
clocks = <&osc24M>;
|
||||
};
|
||||
|
||||
/* dummy is 200M */
|
||||
cpu: cpu@01c20054 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-cpu-clk";
|
||||
reg = <0x01c20054 0x4>;
|
||||
clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
|
||||
};
|
||||
|
||||
axi: axi@01c20054 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-axi-clk";
|
||||
reg = <0x01c20054 0x4>;
|
||||
clocks = <&cpu>;
|
||||
};
|
||||
|
||||
axi_gates: axi_gates@01c2005c {
|
||||
#clock-cells = <1>;
|
||||
compatible = "allwinner,sun4i-axi-gates-clk";
|
||||
reg = <0x01c2005c 0x4>;
|
||||
clocks = <&axi>;
|
||||
clock-output-names = "axi_dram";
|
||||
};
|
||||
|
||||
ahb: ahb@01c20054 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-ahb-clk";
|
||||
reg = <0x01c20054 0x4>;
|
||||
clocks = <&axi>;
|
||||
};
|
||||
|
||||
ahb_gates: ahb_gates@01c20060 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "allwinner,sun4i-ahb-gates-clk";
|
||||
reg = <0x01c20060 0x8>;
|
||||
clocks = <&ahb>;
|
||||
clock-output-names = "ahb_usb0", "ahb_ehci0",
|
||||
"ahb_ohci0", "ahb_ehci1", "ahb_ohci1", "ahb_ss",
|
||||
"ahb_dma", "ahb_bist", "ahb_mmc0", "ahb_mmc1",
|
||||
"ahb_mmc2", "ahb_mmc3", "ahb_ms", "ahb_nand",
|
||||
"ahb_sdram", "ahb_ace", "ahb_emac", "ahb_ts",
|
||||
"ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_spi3",
|
||||
"ahb_pata", "ahb_sata", "ahb_gps", "ahb_ve",
|
||||
"ahb_tvd", "ahb_tve0", "ahb_tve1", "ahb_lcd0",
|
||||
"ahb_lcd1", "ahb_csi0", "ahb_csi1", "ahb_hdmi",
|
||||
"ahb_de_be0", "ahb_de_be1", "ahb_de_fe0",
|
||||
"ahb_de_fe1", "ahb_mp", "ahb_mali400";
|
||||
};
|
||||
|
||||
apb0: apb0@01c20054 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-apb0-clk";
|
||||
reg = <0x01c20054 0x4>;
|
||||
clocks = <&ahb>;
|
||||
};
|
||||
|
||||
apb0_gates: apb0_gates@01c20068 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "allwinner,sun4i-apb0-gates-clk";
|
||||
reg = <0x01c20068 0x4>;
|
||||
clocks = <&apb0>;
|
||||
clock-output-names = "apb0_codec", "apb0_spdif",
|
||||
"apb0_ac97", "apb0_iis", "apb0_pio", "apb0_ir0",
|
||||
"apb0_ir1", "apb0_keypad";
|
||||
};
|
||||
|
||||
/* dummy is pll62 */
|
||||
apb1_mux: apb1_mux@01c20058 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-apb1-mux-clk";
|
||||
reg = <0x01c20058 0x4>;
|
||||
clocks = <&osc24M>, <&dummy>, <&osc32k>;
|
||||
};
|
||||
|
||||
apb1: apb1@01c20058 {
|
||||
#clock-cells = <0>;
|
||||
compatible = "allwinner,sun4i-apb1-clk";
|
||||
reg = <0x01c20058 0x4>;
|
||||
clocks = <&apb1_mux>;
|
||||
};
|
||||
|
||||
apb1_gates: apb1_gates@01c2006c {
|
||||
#clock-cells = <1>;
|
||||
compatible = "allwinner,sun4i-apb1-gates-clk";
|
||||
reg = <0x01c2006c 0x4>;
|
||||
clocks = <&apb1>;
|
||||
clock-output-names = "apb1_i2c0", "apb1_i2c1",
|
||||
"apb1_i2c2", "apb1_can", "apb1_scr",
|
||||
"apb1_ps20", "apb1_ps21", "apb1_uart0",
|
||||
"apb1_uart1", "apb1_uart2", "apb1_uart3",
|
||||
"apb1_uart4", "apb1_uart5", "apb1_uart6",
|
||||
"apb1_uart7";
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x01c20000 0x300000>;
|
||||
ranges;
|
||||
|
||||
timer@01c20c00 {
|
||||
compatible = "allwinner,sunxi-timer";
|
||||
reg = <0x01c20c00 0x90>;
|
||||
interrupts = <22>;
|
||||
clocks = <&osc24M>;
|
||||
};
|
||||
|
||||
wdt: watchdog@01c20c90 {
|
||||
compatible = "allwinner,sunxi-wdt";
|
||||
reg = <0x01c20c90 0x10>;
|
||||
};
|
||||
|
||||
intc: interrupt-controller@01c20400 {
|
||||
compatible = "allwinner,sunxi-ic";
|
||||
reg = <0x01c20400 0x400>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
};
|
||||
|
||||
uart1: serial@01c28400 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x01c28400 0x400>;
|
||||
interrupts = <2>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&apb1_gates 17>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart3: serial@01c28c00 {
|
||||
compatible = "snps,dw-apb-uart";
|
||||
reg = <0x01c28c00 0x400>;
|
||||
interrupts = <4>;
|
||||
reg-shift = <2>;
|
||||
reg-io-width = <4>;
|
||||
clocks = <&apb1_gates 19>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
Loading…
Reference in New Issue