arm64: dts: imx8m: add the rpmsg support
Add the imx8mq/imx8mm rpmsg support. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>5.4-rM2-2.2.x-imx-squashed
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cd8bc8edd7
commit
6945d59d54
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@ -21,9 +21,9 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb
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dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb imx8mm-evk-rpmsg.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb imx8mq-evk-rpmsg.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mq-hummingboard-pulse.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mq-librem5-devkit.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mq-nitrogen.dtb
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@ -0,0 +1,57 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright 2019 NXP
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*/
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/dts-v1/;
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#include "imx8mm-evk.dts"
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/ {
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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m4_reserved: m4@0x80000000 {
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no-map;
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reg = <0 0x80000000 0 0x1000000>;
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};
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rpmsg_reserved: rpmsg@0xb8000000 {
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no-map;
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reg = <0 0xb8000000 0 0x400000>;
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};
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};
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};
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/*
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* ATTENTION: M4 may use IPs like below
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* ECSPI0/ECSPI2, GPIO1/GPIO5, GPT1, I2C3, I2S3, WDOG1, UART4, PWM3, SDMA1
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*/
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&i2c3 {
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status = "disabled";
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};
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&rpmsg{
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/*
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* 64K for one rpmsg instance:
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* --0xb8000000~0xb800ffff: pingpong
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*/
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vdev-nums = <1>;
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reg = <0x0 0xb8000000 0x0 0x10000>;
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status = "okay";
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};
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&sdma1{
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status = "disabled";
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};
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&uart4 {
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status = "disabled";
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};
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&sdma3 {
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status = "disabled";
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};
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@ -690,6 +690,15 @@
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status = "disabled";
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};
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mu: mu@30aa0000 {
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compatible = "fsl,imx8mm-mu", "fsl,imx6sx-mu";
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reg = <0x30aa0000 0x10000>;
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interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX8MM_CLK_MU_ROOT>;
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clock-names = "mu";
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#mbox-cells = <2>;
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};
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usdhc1: mmc@30b40000 {
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compatible = "fsl,imx8mm-usdhc", "fsl,imx7d-usdhc";
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reg = <0x30b40000 0x10000>;
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@ -866,4 +875,18 @@
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interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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rpmsg: rpmsg{
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compatible = "fsl,imx8mq-rpmsg";
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/* up to now, the following channels are used in imx rpmsg
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* - tx1/rx1: messages channel.
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* - general interrupt1: remote proc finish re-init rpmsg stack
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* when A core is partition reset.
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*/
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mbox-names = "tx", "rx", "rxdb";
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mboxes = <&mu 0 1
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&mu 1 1
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&mu 3 1>;
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status = "disabled";
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};
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};
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@ -0,0 +1,62 @@
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// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/*
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* Copyright 2019 NXP
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*/
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/dts-v1/;
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#include "imx8mq-evk.dts"
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/ {
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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m4_reserved: m4@0x80000000 {
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no-map;
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reg = <0 0x80000000 0 0x1000000>;
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};
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rpmsg_reserved: rpmsg@0xb8000000 {
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no-map;
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reg = <0 0xb8000000 0 0x400000>;
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};
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};
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};
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/*
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* Regarding to the HW conflications, the following module should be disabled
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* when M4 is running on evk board.
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* gpt1, i2c2, pwm4, tmu, uart2, wdog3
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*/
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&i2c2 {
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status = "disabled";
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};
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&pwm4 {
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status = "disabled";
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};
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&rpmsg{
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/*
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* 64K for one rpmsg instance:
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* --0xb8000000~0xb800ffff: pingpong
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*/
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vdev-nums = <1>;
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reg = <0x0 0xb8000000 0x0 0x10000>;
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status = "okay";
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};
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&tmu {
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status = "disabled";
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};
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&uart2 {
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status = "disabled";
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};
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&wdog3{
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status = "disabled";
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};
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@ -845,6 +845,15 @@
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status = "disabled";
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};
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mu: mu@30aa0000 {
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compatible = "fsl,imx8mq-mu", "fsl,imx6sx-mu";
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reg = <0x30aa0000 0x10000>;
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interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX8MQ_CLK_MU_ROOT>;
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clock-names = "mu";
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#mbox-cells = <2>;
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};
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usdhc1: mmc@30b40000 {
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compatible = "fsl,imx8mq-usdhc",
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"fsl,imx7d-usdhc";
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@ -1125,4 +1134,18 @@
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status = "disabled";
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};
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};
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rpmsg: rpmsg{
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compatible = "fsl,imx8mq-rpmsg";
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/* up to now, the following channels are used in imx rpmsg
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* - tx1/rx1: messages channel.
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* - general interrupt1: remote proc finish re-init rpmsg stack
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* when A core is partition reset.
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*/
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mbox-names = "tx", "rx", "rxdb";
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mboxes = <&mu 0 1
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&mu 1 1
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&mu 3 1>;
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status = "disabled";
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};
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};
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