KVM: PPC: Book3S HV: Do SLB load/unload with guest LPCR value loaded
This moves the code that loads and unloads the guest SLB values so that it is done while the guest LPCR value is loaded in the LPCR register. The reason for doing this is that on POWER9, the behaviour of the slbmte instruction depends on the LPCR[UPRT] bit. If UPRT is 1, as it is for a radix host (or guest), the SLB index is truncated to 2 bits. This means that for a HPT guest on a radix host, the SLB was not being loaded correctly, causing the guest to crash. The SLB is now loaded much later in the guest entry path, after the LPCR is loaded, which for a secondary thread is after it sees that the primary thread has switched the MMU to the guest. The loop that waits for the primary thread has a branch out to the exit code that is taken if it sees that other threads have commenced exiting the guest. Since we have now not loaded the SLB at this point, we make this path branch to a new label 'guest_bypass' and we move the SLB unload code to before this label. Signed-off-by: Paul Mackerras <paulus@ozlabs.org>hifive-unleashed-5.1
Paul Mackerras
parent
43ff3f6523
commit
6964e6a4e4
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@ -617,13 +617,6 @@ kvmppc_hv_entry:
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lbz r0, KVM_RADIX(r9)
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cmpwi cr7, r0, 0
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/* Clear out SLB if hash */
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bne cr7, 2f
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li r6,0
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slbmte r6,r6
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slbia
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ptesync
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2:
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/*
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* POWER7/POWER8 host -> guest partition switch code.
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* We don't have to lock against concurrent tlbies,
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@ -738,19 +731,6 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
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10: cmpdi r4, 0
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beq kvmppc_primary_no_guest
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kvmppc_got_guest:
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/* Load up guest SLB entries (N.B. slb_max will be 0 for radix) */
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lwz r5,VCPU_SLB_MAX(r4)
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cmpwi r5,0
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beq 9f
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mtctr r5
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addi r6,r4,VCPU_SLB
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1: ld r8,VCPU_SLB_E(r6)
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ld r9,VCPU_SLB_V(r6)
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slbmte r9,r8
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addi r6,r6,VCPU_SLB_SIZE
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bdnz 1b
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9:
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/* Increment yield count if they have a VPA */
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ld r3, VCPU_VPA(r4)
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cmpdi r3, 0
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@ -1017,6 +997,29 @@ ALT_FTR_SECTION_END_IFCLR(CPU_FTR_ARCH_300)
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cmpdi r3, 512 /* 1 microsecond */
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blt hdec_soon
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/* For hash guest, clear out and reload the SLB */
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ld r6, VCPU_KVM(r4)
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lbz r0, KVM_RADIX(r6)
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cmpwi r0, 0
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bne 9f
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li r6, 0
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slbmte r6, r6
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slbia
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ptesync
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/* Load up guest SLB entries (N.B. slb_max will be 0 for radix) */
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lwz r5,VCPU_SLB_MAX(r4)
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cmpwi r5,0
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beq 9f
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mtctr r5
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addi r6,r4,VCPU_SLB
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1: ld r8,VCPU_SLB_E(r6)
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ld r9,VCPU_SLB_V(r6)
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slbmte r9,r8
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addi r6,r6,VCPU_SLB_SIZE
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bdnz 1b
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9:
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#ifdef CONFIG_KVM_XICS
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/* We are entering the guest on that thread, push VCPU to XIVE */
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ld r10, HSTATE_XIVE_TIMA_PHYS(r13)
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@ -1193,7 +1196,7 @@ hdec_soon:
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addi r3, r4, VCPU_TB_RMEXIT
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bl kvmhv_accumulate_time
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#endif
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b guest_exit_cont
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b guest_bypass
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/******************************************************************************
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* *
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@ -1481,6 +1484,35 @@ mc_cont:
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1:
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#endif /* CONFIG_KVM_XICS */
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/* For hash guest, read the guest SLB and save it away */
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ld r5, VCPU_KVM(r9)
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lbz r0, KVM_RADIX(r5)
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li r5, 0
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cmpwi r0, 0
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bne 3f /* for radix, save 0 entries */
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lwz r0,VCPU_SLB_NR(r9) /* number of entries in SLB */
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mtctr r0
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li r6,0
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addi r7,r9,VCPU_SLB
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1: slbmfee r8,r6
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andis. r0,r8,SLB_ESID_V@h
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beq 2f
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add r8,r8,r6 /* put index in */
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slbmfev r3,r6
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std r8,VCPU_SLB_E(r7)
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std r3,VCPU_SLB_V(r7)
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addi r7,r7,VCPU_SLB_SIZE
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addi r5,r5,1
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2: addi r6,r6,1
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bdnz 1b
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/* Finally clear out the SLB */
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li r0,0
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slbmte r0,r0
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slbia
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ptesync
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3: stw r5,VCPU_SLB_MAX(r9)
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guest_bypass:
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mr r3, r12
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/* Increment exit count, poke other threads to exit */
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bl kvmhv_commence_exit
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@ -1501,31 +1533,6 @@ mc_cont:
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ori r6,r6,1
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mtspr SPRN_CTRLT,r6
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4:
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/* Check if we are running hash or radix and store it in cr2 */
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ld r5, VCPU_KVM(r9)
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lbz r0, KVM_RADIX(r5)
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cmpwi cr2,r0,0
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/* Read the guest SLB and save it away */
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li r5, 0
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bne cr2, 3f /* for radix, save 0 entries */
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lwz r0,VCPU_SLB_NR(r9) /* number of entries in SLB */
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mtctr r0
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li r6,0
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addi r7,r9,VCPU_SLB
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1: slbmfee r8,r6
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andis. r0,r8,SLB_ESID_V@h
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beq 2f
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add r8,r8,r6 /* put index in */
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slbmfev r3,r6
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std r8,VCPU_SLB_E(r7)
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std r3,VCPU_SLB_V(r7)
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addi r7,r7,VCPU_SLB_SIZE
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addi r5,r5,1
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2: addi r6,r6,1
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bdnz 1b
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3: stw r5,VCPU_SLB_MAX(r9)
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/*
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* Save the guest PURR/SPURR
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*/
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@ -1803,7 +1810,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
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ld r5, VCPU_KVM(r9)
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lbz r0, KVM_RADIX(r5)
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cmpwi cr2, r0, 0
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beq cr2, 3f
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beq cr2, 4f
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/* Radix: Handle the case where the guest used an illegal PID */
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LOAD_REG_ADDR(r4, mmu_base_pid)
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@ -1839,15 +1846,9 @@ END_FTR_SECTION_IFSET(CPU_FTR_ARCH_300)
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BEGIN_FTR_SECTION
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PPC_INVALIDATE_ERAT
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END_FTR_SECTION_IFSET(CPU_FTR_POWER9_DD1)
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b 4f
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4:
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#endif /* CONFIG_PPC_RADIX_MMU */
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/* Hash: clear out SLB */
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3: li r5,0
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slbmte r5,r5
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slbia
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ptesync
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4:
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/*
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* POWER7/POWER8 guest -> host partition switch code.
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* We don't have to lock against tlbies but we do
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