Merge remote-tracking branch 'origin/irq/gic-v3-nmi-ns' into irq/irqchip-next
Signed-off-by: Marc Zyngier <maz@kernel.org>
This commit is contained in:
commit
696966ec06
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@ -153,7 +153,7 @@ static inline bool gic_prio_masking_enabled(void)
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static inline void gic_pmr_mask_irqs(void)
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{
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BUILD_BUG_ON(GICD_INT_DEF_PRI < (GIC_PRIO_IRQOFF |
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BUILD_BUG_ON(GICD_INT_DEF_PRI < (__GIC_PRIO_IRQOFF |
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GIC_PRIO_PSR_I_SET));
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BUILD_BUG_ON(GICD_INT_DEF_PRI >= GIC_PRIO_IRQON);
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/*
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@ -162,6 +162,12 @@ static inline void gic_pmr_mask_irqs(void)
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* are applied to IRQ priorities
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*/
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BUILD_BUG_ON((0x80 | (GICD_INT_DEF_PRI >> 1)) >= GIC_PRIO_IRQON);
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/*
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* Same situation as above, but now we make sure that we can mask
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* regular interrupts.
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*/
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BUILD_BUG_ON((0x80 | (GICD_INT_DEF_PRI >> 1)) < (__GIC_PRIO_IRQOFF_NS |
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GIC_PRIO_PSR_I_SET));
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gic_write_pmr(GIC_PRIO_IRQOFF);
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}
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@ -31,9 +31,21 @@
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* interrupt disabling temporarily does not rely on IRQ priorities.
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*/
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#define GIC_PRIO_IRQON 0xe0
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#define GIC_PRIO_IRQOFF (GIC_PRIO_IRQON & ~0x80)
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#define __GIC_PRIO_IRQOFF (GIC_PRIO_IRQON & ~0x80)
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#define __GIC_PRIO_IRQOFF_NS 0xa0
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#define GIC_PRIO_PSR_I_SET (1 << 4)
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#define GIC_PRIO_IRQOFF \
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({ \
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extern struct static_key_false gic_nonsecure_priorities;\
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u8 __prio = __GIC_PRIO_IRQOFF; \
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\
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if (static_branch_unlikely(&gic_nonsecure_priorities)) \
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__prio = __GIC_PRIO_IRQOFF_NS; \
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\
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__prio; \
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})
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/* Additional SPSR bits not exposed in the UABI */
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#define PSR_MODE_THREAD_BIT (1 << 0)
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#define PSR_IL_BIT (1 << 20)
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@ -101,6 +101,8 @@ KVM_NVHE_ALIAS(vgic_v3_cpuif_trap);
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/* Static key checked in pmr_sync(). */
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#ifdef CONFIG_ARM64_PSEUDO_NMI
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KVM_NVHE_ALIAS(gic_pmr_sync);
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/* Static key checked in GIC_PRIO_IRQOFF. */
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KVM_NVHE_ALIAS(gic_nonsecure_priorities);
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#endif
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/* EL2 exception handling */
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@ -75,16 +75,14 @@ static DEFINE_STATIC_KEY_TRUE(supports_deactivate_key);
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*
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* If SCR_EL3.FIQ == 1, the values writen to/read from PMR and RPR at non-secure
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* EL1 are subject to a similar operation thus matching the priorities presented
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* from the (re)distributor when security is enabled.
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* from the (re)distributor when security is enabled. When SCR_EL3.FIQ == 0,
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* these values are unchanched by the GIC.
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*
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* see GICv3/GICv4 Architecture Specification (IHI0069D):
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* - section 4.8.1 Non-secure accesses to register fields for Secure interrupt
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* priorities.
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* - Figure 4-7 Secure read of the priority field for a Non-secure Group 1
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* interrupt.
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*
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* For now, we only support pseudo-NMIs if we have non-secure view of
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* priorities.
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*/
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static DEFINE_STATIC_KEY_FALSE(supports_pseudo_nmis);
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@ -97,6 +95,9 @@ static DEFINE_STATIC_KEY_FALSE(supports_pseudo_nmis);
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DEFINE_STATIC_KEY_FALSE(gic_pmr_sync);
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EXPORT_SYMBOL(gic_pmr_sync);
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DEFINE_STATIC_KEY_FALSE(gic_nonsecure_priorities);
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EXPORT_SYMBOL(gic_nonsecure_priorities);
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/* ppi_nmi_refs[n] == number of cpus having ppi[n + 16] set as NMI */
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static refcount_t *ppi_nmi_refs;
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@ -932,14 +933,20 @@ static void gic_cpu_sys_reg_init(void)
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/* Set priority mask register */
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if (!gic_prio_masking_enabled()) {
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write_gicreg(DEFAULT_PMR_VALUE, ICC_PMR_EL1);
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} else {
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} else if (gic_supports_nmi()) {
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/*
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* Mismatch configuration with boot CPU, the system is likely
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* to die as interrupt masking will not work properly on all
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* CPUs
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*
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* The boot CPU calls this function before enabling NMI support,
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* and as a result we'll never see this warning in the boot path
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* for that CPU.
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*/
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WARN_ON(gic_supports_nmi() && group0 &&
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!gic_dist_security_disabled());
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if (static_branch_unlikely(&gic_nonsecure_priorities))
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WARN_ON(!group0 || gic_dist_security_disabled());
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else
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WARN_ON(group0 && !gic_dist_security_disabled());
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}
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/*
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@ -1544,11 +1551,6 @@ static void gic_enable_nmi_support(void)
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if (!gic_prio_masking_enabled())
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return;
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if (gic_has_group0() && !gic_dist_security_disabled()) {
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pr_warn("SCR_EL3.FIQ is cleared, cannot enable use of pseudo-NMIs\n");
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return;
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}
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ppi_nmi_refs = kcalloc(gic_data.ppi_nr, sizeof(*ppi_nmi_refs), GFP_KERNEL);
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if (!ppi_nmi_refs)
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return;
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@ -1564,8 +1566,38 @@ static void gic_enable_nmi_support(void)
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if (gic_read_ctlr() & ICC_CTLR_EL1_PMHE_MASK)
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static_branch_enable(&gic_pmr_sync);
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pr_info("%s ICC_PMR_EL1 synchronisation\n",
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static_branch_unlikely(&gic_pmr_sync) ? "Forcing" : "Relaxing");
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pr_info("Pseudo-NMIs enabled using %s ICC_PMR_EL1 synchronisation\n",
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static_branch_unlikely(&gic_pmr_sync) ? "forced" : "relaxed");
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/*
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* How priority values are used by the GIC depends on two things:
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* the security state of the GIC (controlled by the GICD_CTRL.DS bit)
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* and if Group 0 interrupts can be delivered to Linux in the non-secure
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* world as FIQs (controlled by the SCR_EL3.FIQ bit). These affect the
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* the ICC_PMR_EL1 register and the priority that software assigns to
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* interrupts:
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*
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* GICD_CTRL.DS | SCR_EL3.FIQ | ICC_PMR_EL1 | Group 1 priority
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* -----------------------------------------------------------
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* 1 | - | unchanged | unchanged
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* -----------------------------------------------------------
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* 0 | 1 | non-secure | non-secure
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* -----------------------------------------------------------
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* 0 | 0 | unchanged | non-secure
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*
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* where non-secure means that the value is right-shifted by one and the
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* MSB bit set, to make it fit in the non-secure priority range.
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*
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* In the first two cases, where ICC_PMR_EL1 and the interrupt priority
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* are both either modified or unchanged, we can use the same set of
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* priorities.
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*
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* In the last case, where only the interrupt priorities are modified to
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* be in the non-secure range, we use a different PMR value to mask IRQs
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* and the rest of the values that we use remain unchanged.
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*/
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if (gic_has_group0() && !gic_dist_security_disabled())
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static_branch_enable(&gic_nonsecure_priorities);
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static_branch_enable(&supports_pseudo_nmis);
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