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s3c2410fb: adds pixclock to s3c2410fb_display 

This patch adds pixelclock field to the s3c2410fb_display structure and make
use of it in the driver.

The Bast machine defined 9 modes but pixclock and margin values are defined
only for the 640x480 modes so I removed other modes.

This patch also fixes wrong display type constant for the SMDK2440 board.

Signed-off-by: Krzysztof Helt <krzysztof.h1@wp.pl>
Signed-off-by: Antonino Daplas <adaplas@gmail.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
hifive-unleashed-5.1
Krzysztof Helt 2007-10-16 01:29:06 -07:00 committed by Linus Torvalds
parent 9fa7bc016a
commit 69816699fa
8 changed files with 28 additions and 136 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
arch/arm/mach-s3c2410/mach-amlm5900.c
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@ -174,6 +174,7 @@ static struct s3c2410fb_display __initdata amlm5900_lcd_info = {
.type = S3C2410_LCDCON1_STN4,
.pixclock = 680000, /* HCLK = 100MHz */
.xres = 160,
.yres = 160,
.bpp = 4,

112
arch/arm/mach-s3c2410/mach-bast.c
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@ -473,25 +473,7 @@ static struct s3c2410fb_display __initdata bast_lcd_info[] = {
.width = 640,
.height = 480,
.xres = 320,
.yres = 240,
.left_margin = 40,
.right_margin = 20,
.hsync_len = 88,
.upper_margin = 30,
.lower_margin = 32,
.vsync_len = 3,
.bpp = 4,
.lcdcon1 = 0x00000176,
.lcdcon5 = 0x00014b02,
},
{
.type = S3C2410_LCDCON1_TFT,
.width = 640,
.height = 480,
.pixclock = 33333,
.xres = 640,
.yres = 480,
.bpp = 4,
@ -510,42 +492,7 @@ static struct s3c2410fb_display __initdata bast_lcd_info[] = {
.width = 640,
.height = 480,
.xres = 800,
.yres = 600,
.bpp = 4,
.left_margin = 40,
.right_margin = 20,
.hsync_len = 88,
.upper_margin = 30,
.lower_margin = 32,
.vsync_len = 3,
.lcdcon1 = 0x00000176,
.lcdcon5 = 0x00014b02,
},
{
.type = S3C2410_LCDCON1_TFT,
.width = 640,
.height = 480,
.xres = 320,
.yres = 240,
.bpp = 8,
.left_margin = 40,
.right_margin = 20,
.hsync_len = 88,
.upper_margin = 30,
.lower_margin = 32,
.vsync_len = 3,
.lcdcon1 = 0x00000176,
.lcdcon5 = 0x00014b02,
},
{
.type = S3C2410_LCDCON1_TFT,
.width = 640,
.height = 480,
.pixclock = 33333,
.xres = 640,
.yres = 480,
.bpp = 8,
@ -564,42 +511,7 @@ static struct s3c2410fb_display __initdata bast_lcd_info[] = {
.width = 640,
.height = 480,
.xres = 800,
.yres = 600,
.bpp = 8,
.left_margin = 40,
.right_margin = 20,
.hsync_len = 88,
.upper_margin = 30,
.lower_margin = 32,
.vsync_len = 3,
.lcdcon1 = 0x00000176,
.lcdcon5 = 0x00014b02,
},
{
.type = S3C2410_LCDCON1_TFT,
.width = 640,
.height = 480,
.xres = 320,
.yres = 240,
.bpp = 16,
.left_margin = 40,
.right_margin = 20,
.hsync_len = 88,
.upper_margin = 30,
.lower_margin = 32,
.vsync_len = 3,
.lcdcon1 = 0x00000176,
.lcdcon5 = 0x00014b02,
},
{
.type = S3C2410_LCDCON1_TFT,
.width = 640,
.height = 480,
.pixclock = 33333,
.xres = 640,
.yres = 480,
.bpp = 16,
@ -610,24 +522,6 @@ static struct s3c2410fb_display __initdata bast_lcd_info[] = {
.lower_margin = 32,
.vsync_len = 3,
.lcdcon1 = 0x00000176,
.lcdcon5 = 0x00014b02,
},
{
.type = S3C2410_LCDCON1_TFT,
.width = 640,
.height = 480,
.xres = 800,
.yres = 600,
.bpp = 16,
.left_margin = 40,
.right_margin = 20,
.hsync_len = 88,
.upper_margin = 30,
.lower_margin = 32,
.vsync_len = 3,
.lcdcon1 = 0x00000176,
.lcdcon5 = 0x00014b02,
},

1
arch/arm/mach-s3c2410/mach-h1940.c
View File

@ -145,6 +145,7 @@ static struct s3c2410fb_display h1940_lcd __initdata = {
.type = S3C2410_LCDCON1_TFT,
.width = 240,
.height = 320,
.pixclock = 260000,
.xres = 240,
.yres = 320,
.bpp = 16,

3
arch/arm/mach-s3c2410/mach-qt2410.c
View File

@ -112,6 +112,7 @@ static struct s3c2410fb_display qt2410_lcd_cfg[] __initdata = {
.width = 640,
.height = 480,
.pixclock = 40000, /* HCLK/4 */
.xres = 640,
.yres = 480,
.bpp = 16,
@ -137,6 +138,7 @@ static struct s3c2410fb_display qt2410_lcd_cfg[] __initdata = {
.type = S3C2410_LCDCON1_TFT,
.width = 480,
.height = 640,
.pixclock = 40000, /* HCLK/4 */
.xres = 480,
.yres = 640,
.bpp = 16,
@ -162,6 +164,7 @@ static struct s3c2410fb_display qt2410_lcd_cfg[] __initdata = {
.type = S3C2410_LCDCON1_TFT,
.width = 240,
.height = 320,
.pixclock = 100000, /* HCLK/10 */
.xres = 240,
.yres = 320,
.bpp = 16,

1
arch/arm/mach-s3c2440/mach-rx3715.c
View File

@ -123,6 +123,7 @@ static struct s3c2410fb_display rx3715_lcdcfg __initdata = {
.width = 240,
.height = 320,
.pixclock = 260000,
.xres = 240,
.yres = 320,
.bpp = 16,

3
arch/arm/mach-s3c2440/mach-smdk2440.c
View File

@ -115,11 +115,12 @@ static struct s3c2410fb_display smdk2440_lcd_cfg __initdata = {
S3C2410_LCDCON5_PWREN |
S3C2410_LCDCON5_HWSWP,
.type = S3C2410_LCDCON1_TFT16BPP,
.type = S3C2410_LCDCON1_TFT,
.width = 240,
.height = 320,
.pixclock = 166667, /* HCLK 60 MHz, divisor 10 */
.xres = 240,
.yres = 320,
.bpp = 16,

42
drivers/video/s3c2410fb.c
View File

@ -199,6 +199,7 @@ static int s3c2410fb_check_var(struct fb_var_screeninfo *var,
var->width = display->width;
/* copy lcd settings */
var->pixclock = display->pixclock;
var->left_margin = display->left_margin;
var->right_margin = display->right_margin;
var->upper_margin = display->upper_margin;
@ -297,10 +298,6 @@ static void s3c2410fb_calculate_stn_lcd_regs(const struct fb_info *info,
unsigned wdly = (var->left_margin >> 4) - 1;
unsigned wlh = (var->hsync_len >> 4) - 1;
dprintk("%s: var->xres = %d\n", __FUNCTION__, var->xres);
dprintk("%s: var->yres = %d\n", __FUNCTION__, var->yres);
dprintk("%s: var->bpp = %d\n", __FUNCTION__, var->bits_per_pixel);
if (type != S3C2410_LCDCON1_STN4)
hs >>= 1;
@ -359,10 +356,6 @@ static void s3c2410fb_calculate_tft_lcd_regs(const struct fb_info *info,
const struct s3c2410fb_info *fbi = info->par;
const struct fb_var_screeninfo *var = &info->var;
dprintk("%s: var->xres = %d\n", __FUNCTION__, var->xres);
dprintk("%s: var->yres = %d\n", __FUNCTION__, var->yres);
dprintk("%s: var->bpp = %d\n", __FUNCTION__, var->bits_per_pixel);
regs->lcdcon1 &= ~S3C2410_LCDCON1_MODEMASK;
switch (var->bits_per_pixel) {
@ -427,28 +420,25 @@ static void s3c2410fb_activate_var(struct fb_info *info)
void __iomem *regs = fbi->io;
int type = fbi->regs.lcdcon1 & S3C2410_LCDCON1_TFT;
struct fb_var_screeninfo *var = &info->var;
int clkdiv = s3c2410fb_calc_pixclk(fbi, var->pixclock) / 2;
if (var->pixclock > 0) {
int clkdiv = s3c2410fb_calc_pixclk(fbi, var->pixclock);
dprintk("%s: var->xres = %d\n", __FUNCTION__, var->xres);
dprintk("%s: var->yres = %d\n", __FUNCTION__, var->yres);
dprintk("%s: var->bpp = %d\n", __FUNCTION__, var->bits_per_pixel);
if (type == S3C2410_LCDCON1_TFT) {
clkdiv = (clkdiv / 2) - 1;
if (clkdiv < 0)
clkdiv = 0;
} else {
clkdiv = (clkdiv / 2);
if (clkdiv < 2)
clkdiv = 2;
}
fbi->regs.lcdcon1 &= ~S3C2410_LCDCON1_CLKVAL(0x3ff);
fbi->regs.lcdcon1 |= S3C2410_LCDCON1_CLKVAL(clkdiv);
if (type == S3C2410_LCDCON1_TFT) {
s3c2410fb_calculate_tft_lcd_regs(info, &fbi->regs);
--clkdiv;
if (clkdiv < 0)
clkdiv = 0;
} else {
s3c2410fb_calculate_stn_lcd_regs(info, &fbi->regs);
if (clkdiv < 2)
clkdiv = 2;
}
if (type == S3C2410_LCDCON1_TFT)
s3c2410fb_calculate_tft_lcd_regs(info, &fbi->regs);
else
s3c2410fb_calculate_stn_lcd_regs(info, &fbi->regs);
fbi->regs.lcdcon1 &= ~S3C2410_LCDCON1_CLKVAL(0x3ff);
fbi->regs.lcdcon1 |= S3C2410_LCDCON1_CLKVAL(clkdiv);
/* write new registers */

1
include/asm-arm/arch-s3c2410/fb.h
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@ -36,6 +36,7 @@ struct s3c2410fb_display {
unsigned short yres;
unsigned short bpp;
unsigned pixclock; /* pixclock in picoseconds */
unsigned short left_margin; /* value in pixels (TFT) or HCLKs (STN) */
unsigned short right_margin; /* value in pixels (TFT) or HCLKs (STN) */
unsigned short hsync_len; /* value in pixels (TFT) or HCLKs (STN) */