drm/nouveau/fifo/gk104: cosmetic engine->runlist changes
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
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acdf7d4f7e
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69aa40e276
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@ -7,7 +7,7 @@
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struct gk104_fifo_chan {
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struct nvkm_fifo_chan base;
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struct gk104_fifo *fifo;
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int engine;
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int runl;
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struct list_head head;
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bool killed;
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@ -47,38 +47,41 @@ gk104_fifo_uevent_init(struct nvkm_fifo *fifo)
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}
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void
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gk104_fifo_runlist_commit(struct gk104_fifo *fifo, u32 engine)
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gk104_fifo_runlist_commit(struct gk104_fifo *fifo, int runl)
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{
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struct gk104_fifo_engn *engn = &fifo->engine[engine];
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struct gk104_fifo_chan *chan;
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struct nvkm_subdev *subdev = &fifo->base.engine.subdev;
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struct nvkm_device *device = subdev->device;
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struct nvkm_memory *cur;
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struct nvkm_memory *mem;
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int nr = 0;
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int target;
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mutex_lock(&subdev->mutex);
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cur = engn->runlist[engn->cur_runlist];
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engn->cur_runlist = !engn->cur_runlist;
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mem = fifo->runlist[runl].mem[fifo->runlist[runl].next];
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fifo->runlist[runl].next = !fifo->runlist[runl].next;
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nvkm_kmap(cur);
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list_for_each_entry(chan, &engn->chan, head) {
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nvkm_wo32(cur, (nr * 8) + 0, chan->base.chid);
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nvkm_wo32(cur, (nr * 8) + 4, 0x00000000);
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nvkm_kmap(mem);
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list_for_each_entry(chan, &fifo->runlist[runl].chan, head) {
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nvkm_wo32(mem, (nr * 8) + 0, chan->base.chid);
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nvkm_wo32(mem, (nr * 8) + 4, 0x00000000);
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nr++;
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}
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nvkm_done(cur);
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nvkm_done(mem);
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target = (nvkm_memory_target(cur) == NVKM_MEM_TARGET_HOST) ? 0x3 : 0x0;
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if (nvkm_memory_target(mem) == NVKM_MEM_TARGET_VRAM)
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target = 0;
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else
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target = 3;
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nvkm_wr32(device, 0x002270, (nvkm_memory_addr(cur) >> 12) |
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nvkm_wr32(device, 0x002270, (nvkm_memory_addr(mem) >> 12) |
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(target << 28));
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nvkm_wr32(device, 0x002274, (engine << 20) | nr);
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nvkm_wr32(device, 0x002274, (runl << 20) | nr);
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if (wait_event_timeout(engn->wait, !(nvkm_rd32(device, 0x002284 +
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(engine * 0x08)) & 0x00100000),
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msecs_to_jiffies(2000)) == 0)
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nvkm_error(subdev, "runlist %d update timeout\n", engine);
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if (wait_event_timeout(fifo->runlist[runl].wait,
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!(nvkm_rd32(device, 0x002284 + (runl * 0x08))
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& 0x00100000),
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msecs_to_jiffies(2000)) == 0)
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nvkm_error(subdev, "runlist %d update timeout\n", runl);
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mutex_unlock(&subdev->mutex);
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}
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@ -94,7 +97,7 @@ void
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gk104_fifo_runlist_insert(struct gk104_fifo *fifo, struct gk104_fifo_chan *chan)
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{
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mutex_lock(&fifo->base.engine.subdev.mutex);
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list_add_tail(&chan->head, &fifo->engine[chan->engine].chan);
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list_add_tail(&chan->head, &fifo->runlist[chan->runl].chan);
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mutex_unlock(&fifo->base.engine.subdev.mutex);
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}
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@ -199,7 +202,7 @@ gk104_fifo_intr_sched_ctxsw(struct gk104_fifo *fifo)
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u32 engn;
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spin_lock_irqsave(&fifo->base.lock, flags);
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for (engn = 0; engn < ARRAY_SIZE(fifo->engine); engn++) {
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for (engn = 0; engn < ARRAY_SIZE(fifo->runlist); engn++) {
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u32 stat = nvkm_rd32(device, 0x002640 + (engn * 0x08));
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u32 busy = (stat & 0x80000000);
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u32 next = (stat & 0x0fff0000) >> 16;
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@ -211,7 +214,7 @@ gk104_fifo_intr_sched_ctxsw(struct gk104_fifo *fifo)
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(void)save;
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if (busy && chsw) {
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list_for_each_entry(chan, &fifo->engine[engn].chan, head) {
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list_for_each_entry(chan, &fifo->runlist[engn].chan, head) {
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if (chan->base.chid == chid) {
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engine = gk104_fifo_engine(fifo, engn);
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if (!engine)
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@ -541,10 +544,10 @@ gk104_fifo_intr_runlist(struct gk104_fifo *fifo)
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struct nvkm_device *device = fifo->base.engine.subdev.device;
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u32 mask = nvkm_rd32(device, 0x002a00);
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while (mask) {
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u32 engn = __ffs(mask);
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wake_up(&fifo->engine[engn].wait);
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nvkm_wr32(device, 0x002a00, 1 << engn);
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mask &= ~(1 << engn);
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int runl = __ffs(mask);
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wake_up(&fifo->runlist[runl].wait);
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nvkm_wr32(device, 0x002a00, 1 << runl);
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mask &= ~(1 << runl);
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}
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}
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@ -669,21 +672,21 @@ gk104_fifo_oneinit(struct nvkm_fifo *base)
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fifo->pbdma_nr = hweight32(nvkm_rd32(device, 0x000204));
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nvkm_debug(subdev, "%d PBDMA(s)\n", fifo->pbdma_nr);
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for (i = 0; i < ARRAY_SIZE(fifo->engine); i++) {
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for (i = 0; i < ARRAY_SIZE(fifo->runlist); i++) {
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ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST,
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0x8000, 0x1000, false,
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&fifo->engine[i].runlist[0]);
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&fifo->runlist[i].mem[0]);
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if (ret)
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return ret;
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ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST,
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0x8000, 0x1000, false,
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&fifo->engine[i].runlist[1]);
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&fifo->runlist[i].mem[1]);
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if (ret)
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return ret;
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init_waitqueue_head(&fifo->engine[i].wait);
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INIT_LIST_HEAD(&fifo->engine[i].chan);
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init_waitqueue_head(&fifo->runlist[i].wait);
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INIT_LIST_HEAD(&fifo->runlist[i].chan);
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}
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ret = nvkm_memory_new(device, NVKM_MEM_TARGET_INST,
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@ -739,9 +742,9 @@ gk104_fifo_dtor(struct nvkm_fifo *base)
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nvkm_vm_put(&fifo->user.bar);
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nvkm_memory_del(&fifo->user.mem);
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for (i = 0; i < ARRAY_SIZE(fifo->engine); i++) {
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nvkm_memory_del(&fifo->engine[i].runlist[1]);
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nvkm_memory_del(&fifo->engine[i].runlist[0]);
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for (i = 0; i < ARRAY_SIZE(fifo->runlist); i++) {
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nvkm_memory_del(&fifo->runlist[i].mem[1]);
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nvkm_memory_del(&fifo->runlist[i].mem[0]);
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}
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return fifo;
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@ -6,13 +6,6 @@
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#include <subdev/mmu.h>
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struct gk104_fifo_chan;
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struct gk104_fifo_engn {
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struct nvkm_memory *runlist[2];
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int cur_runlist;
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wait_queue_head_t wait;
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struct list_head chan;
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};
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struct gk104_fifo {
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struct nvkm_fifo base;
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@ -23,7 +16,13 @@ struct gk104_fifo {
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int pbdma_nr;
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struct gk104_fifo_engn engine[7];
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struct {
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struct nvkm_memory *mem[2];
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int next;
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wait_queue_head_t wait;
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struct list_head chan;
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} runlist[7];
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struct {
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struct nvkm_memory *mem;
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struct nvkm_vma bar;
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@ -41,7 +40,7 @@ void gk104_fifo_uevent_init(struct nvkm_fifo *);
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void gk104_fifo_uevent_fini(struct nvkm_fifo *);
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void gk104_fifo_runlist_insert(struct gk104_fifo *, struct gk104_fifo_chan *);
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void gk104_fifo_runlist_remove(struct gk104_fifo *, struct gk104_fifo_chan *);
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void gk104_fifo_runlist_commit(struct gk104_fifo *, u32 engine);
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void gk104_fifo_runlist_commit(struct gk104_fifo *, int runl);
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static inline u64
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gk104_fifo_engine_subdev(int engine)
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@ -155,7 +155,7 @@ gk104_fifo_gpfifo_fini(struct nvkm_fifo_chan *base)
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gk104_fifo_runlist_remove(fifo, chan);
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nvkm_mask(device, 0x800004 + coff, 0x00000800, 0x00000800);
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gk104_fifo_gpfifo_kick(chan);
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gk104_fifo_runlist_commit(fifo, chan->engine);
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gk104_fifo_runlist_commit(fifo, chan->runl);
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}
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nvkm_wr32(device, 0x800000 + coff, 0x00000000);
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@ -170,13 +170,13 @@ gk104_fifo_gpfifo_init(struct nvkm_fifo_chan *base)
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u32 addr = chan->base.inst->addr >> 12;
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u32 coff = chan->base.chid * 8;
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nvkm_mask(device, 0x800004 + coff, 0x000f0000, chan->engine << 16);
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nvkm_mask(device, 0x800004 + coff, 0x000f0000, chan->runl << 16);
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nvkm_wr32(device, 0x800000 + coff, 0x80000000 | addr);
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if (list_empty(&chan->head) && !chan->killed) {
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gk104_fifo_runlist_insert(fifo, chan);
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nvkm_mask(device, 0x800004 + coff, 0x00000400, 0x00000400);
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gk104_fifo_runlist_commit(fifo, chan->engine);
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gk104_fifo_runlist_commit(fifo, chan->runl);
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nvkm_mask(device, 0x800004 + coff, 0x00000400, 0x00000400);
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}
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}
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@ -227,7 +227,7 @@ gk104_fifo_gpfifo_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass,
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return ret;
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/* determine which downstream engines are present */
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for (i = 0, engines = 0; i < ARRAY_SIZE(fifo->engine); i++) {
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for (i = 0, engines = 0; i < ARRAY_SIZE(fifo->runlist); i++) {
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u64 subdevs = gk104_fifo_engine_subdev(i);
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if (!nvkm_device_engine(device, __ffs64(subdevs)))
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continue;
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@ -255,12 +255,12 @@ gk104_fifo_gpfifo_new(struct nvkm_fifo *base, const struct nvkm_oclass *oclass,
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return -ENOMEM;
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*pobject = &chan->base.object;
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chan->fifo = fifo;
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chan->engine = __ffs(args->v0.engine);
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chan->runl = __ffs(args->v0.engine);
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INIT_LIST_HEAD(&chan->head);
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ret = nvkm_fifo_chan_ctor(&gk104_fifo_gpfifo_func, &fifo->base,
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0x1000, 0x1000, true, args->v0.vm, 0,
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gk104_fifo_engine_subdev(chan->engine),
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gk104_fifo_engine_subdev(chan->runl),
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1, fifo->user.bar.offset, 0x200,
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oclass, &chan->base);
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if (ret)
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