drm/i915: Remove the per-ring write list
This is now handled by a global flag to ensure we emit a flush before the next serialisation point (if we failed to queue one previously). Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>hifive-unleashed-5.1
parent
65ce302741
commit
69c2fc8913
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@ -865,8 +865,6 @@ struct drm_i915_gem_object {
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/** This object's place on the active/inactive lists */
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/** This object's place on the active/inactive lists */
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struct list_head ring_list;
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struct list_head ring_list;
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struct list_head mm_list;
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struct list_head mm_list;
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/** This object's place on GPU write list */
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struct list_head gpu_write_list;
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/** This object's place in the batchbuffer or on the eviction list */
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/** This object's place in the batchbuffer or on the eviction list */
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struct list_head exec_list;
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struct list_head exec_list;
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@ -1465,7 +1465,6 @@ i915_gem_object_move_to_inactive(struct drm_i915_gem_object *obj)
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list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
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list_move_tail(&obj->mm_list, &dev_priv->mm.inactive_list);
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BUG_ON(!list_empty(&obj->gpu_write_list));
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BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
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BUG_ON(obj->base.write_domain & ~I915_GEM_GPU_DOMAINS);
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BUG_ON(!obj->active);
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BUG_ON(!obj->active);
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@ -1511,30 +1510,6 @@ i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj)
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return obj->madv == I915_MADV_DONTNEED;
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return obj->madv == I915_MADV_DONTNEED;
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}
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}
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static void
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i915_gem_process_flushing_list(struct intel_ring_buffer *ring,
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uint32_t flush_domains)
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{
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struct drm_i915_gem_object *obj, *next;
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list_for_each_entry_safe(obj, next,
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&ring->gpu_write_list,
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gpu_write_list) {
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if (obj->base.write_domain & flush_domains) {
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uint32_t old_write_domain = obj->base.write_domain;
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obj->base.write_domain = 0;
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list_del_init(&obj->gpu_write_list);
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i915_gem_object_move_to_active(obj, ring,
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i915_gem_next_request_seqno(ring));
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trace_i915_gem_object_change_domain(obj,
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obj->base.read_domains,
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old_write_domain);
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}
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}
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}
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static u32
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static u32
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i915_gem_get_seqno(struct drm_device *dev)
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i915_gem_get_seqno(struct drm_device *dev)
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{
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{
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@ -1637,8 +1612,6 @@ i915_add_request(struct intel_ring_buffer *ring,
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&dev_priv->mm.retire_work, HZ);
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&dev_priv->mm.retire_work, HZ);
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}
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}
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WARN_ON(!list_empty(&ring->gpu_write_list));
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return 0;
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return 0;
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}
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}
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@ -1680,7 +1653,6 @@ static void i915_gem_reset_ring_lists(struct drm_i915_private *dev_priv,
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struct drm_i915_gem_object,
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struct drm_i915_gem_object,
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ring_list);
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ring_list);
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list_del_init(&obj->gpu_write_list);
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i915_gem_object_move_to_inactive(obj);
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i915_gem_object_move_to_inactive(obj);
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}
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}
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}
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}
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@ -2011,11 +1983,6 @@ i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
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u32 seqno;
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u32 seqno;
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int ret;
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int ret;
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/* This function only exists to support waiting for existing rendering,
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* not for emitting required flushes.
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*/
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BUG_ON((obj->base.write_domain & I915_GEM_GPU_DOMAINS) != 0);
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/* If there is rendering queued on the buffer being evicted, wait for
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/* If there is rendering queued on the buffer being evicted, wait for
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* it.
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* it.
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*/
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*/
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@ -2308,26 +2275,14 @@ i915_gem_flush_ring(struct intel_ring_buffer *ring,
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if (ret)
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if (ret)
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return ret;
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return ret;
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if (flush_domains & I915_GEM_GPU_DOMAINS)
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i915_gem_process_flushing_list(ring, flush_domains);
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return 0;
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return 0;
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}
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}
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static int i915_ring_idle(struct intel_ring_buffer *ring)
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static int i915_ring_idle(struct intel_ring_buffer *ring)
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{
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{
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int ret;
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if (list_empty(&ring->active_list))
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if (list_empty(&ring->gpu_write_list) && list_empty(&ring->active_list))
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return 0;
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return 0;
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if (!list_empty(&ring->gpu_write_list)) {
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ret = i915_gem_flush_ring(ring,
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I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS);
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if (ret)
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return ret;
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}
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return i915_wait_seqno(ring, i915_gem_next_request_seqno(ring));
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return i915_wait_seqno(ring, i915_gem_next_request_seqno(ring));
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}
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}
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@ -2343,10 +2298,6 @@ int i915_gpu_idle(struct drm_device *dev)
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if (ret)
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if (ret)
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return ret;
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return ret;
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/* Is the device fubar? */
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if (WARN_ON(!list_empty(&ring->gpu_write_list)))
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return -EBUSY;
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ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID);
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ret = i915_switch_context(ring, NULL, DEFAULT_CONTEXT_ID);
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if (ret)
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if (ret)
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return ret;
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return ret;
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@ -3491,7 +3442,6 @@ struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
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INIT_LIST_HEAD(&obj->gtt_list);
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INIT_LIST_HEAD(&obj->gtt_list);
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INIT_LIST_HEAD(&obj->ring_list);
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INIT_LIST_HEAD(&obj->ring_list);
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INIT_LIST_HEAD(&obj->exec_list);
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INIT_LIST_HEAD(&obj->exec_list);
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INIT_LIST_HEAD(&obj->gpu_write_list);
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obj->madv = I915_MADV_WILLNEED;
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obj->madv = I915_MADV_WILLNEED;
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/* Avoid an unnecessary call to unbind on the first bind. */
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/* Avoid an unnecessary call to unbind on the first bind. */
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obj->map_and_fenceable = true;
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obj->map_and_fenceable = true;
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@ -3912,7 +3862,6 @@ init_ring_lists(struct intel_ring_buffer *ring)
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{
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{
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INIT_LIST_HEAD(&ring->active_list);
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INIT_LIST_HEAD(&ring->active_list);
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INIT_LIST_HEAD(&ring->request_list);
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INIT_LIST_HEAD(&ring->request_list);
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INIT_LIST_HEAD(&ring->gpu_write_list);
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}
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}
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void
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void
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@ -943,9 +943,8 @@ i915_gem_execbuffer_move_to_active(struct list_head *objects,
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struct drm_i915_gem_object *obj;
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struct drm_i915_gem_object *obj;
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list_for_each_entry(obj, objects, exec_list) {
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list_for_each_entry(obj, objects, exec_list) {
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u32 old_read = obj->base.read_domains;
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u32 old_read = obj->base.read_domains;
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u32 old_write = obj->base.write_domain;
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u32 old_write = obj->base.write_domain;
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obj->base.read_domains = obj->base.pending_read_domains;
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obj->base.read_domains = obj->base.pending_read_domains;
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obj->base.write_domain = obj->base.pending_write_domain;
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obj->base.write_domain = obj->base.pending_write_domain;
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@ -955,8 +954,6 @@ i915_gem_execbuffer_move_to_active(struct list_head *objects,
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if (obj->base.write_domain) {
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if (obj->base.write_domain) {
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obj->dirty = 1;
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obj->dirty = 1;
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obj->last_write_seqno = seqno;
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obj->last_write_seqno = seqno;
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list_move_tail(&obj->gpu_write_list,
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&ring->gpu_write_list);
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if (obj->pin_count) /* check for potential scanout */
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if (obj->pin_count) /* check for potential scanout */
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intel_mark_busy(ring->dev, obj);
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intel_mark_busy(ring->dev, obj);
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}
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}
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@ -1002,7 +1002,6 @@ static int intel_init_ring_buffer(struct drm_device *dev,
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ring->dev = dev;
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ring->dev = dev;
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INIT_LIST_HEAD(&ring->active_list);
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INIT_LIST_HEAD(&ring->active_list);
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INIT_LIST_HEAD(&ring->request_list);
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INIT_LIST_HEAD(&ring->request_list);
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INIT_LIST_HEAD(&ring->gpu_write_list);
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ring->size = 32 * PAGE_SIZE;
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ring->size = 32 * PAGE_SIZE;
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init_waitqueue_head(&ring->irq_queue);
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init_waitqueue_head(&ring->irq_queue);
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@ -1473,7 +1472,6 @@ int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
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ring->dev = dev;
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ring->dev = dev;
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INIT_LIST_HEAD(&ring->active_list);
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INIT_LIST_HEAD(&ring->active_list);
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INIT_LIST_HEAD(&ring->request_list);
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INIT_LIST_HEAD(&ring->request_list);
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INIT_LIST_HEAD(&ring->gpu_write_list);
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ring->size = size;
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ring->size = size;
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ring->effective_size = ring->size;
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ring->effective_size = ring->size;
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@ -100,15 +100,6 @@ struct intel_ring_buffer {
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*/
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*/
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struct list_head request_list;
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struct list_head request_list;
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/**
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* List of objects currently pending a GPU write flush.
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*
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* All elements on this list will belong to either the
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* active_list or flushing_list, last_rendering_seqno can
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* be used to differentiate between the two elements.
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*/
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struct list_head gpu_write_list;
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/**
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/**
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* Do we have some not yet emitted requests outstanding?
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* Do we have some not yet emitted requests outstanding?
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*/
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*/
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