bus: ti-sysc: Fix wrong offset for display subsystem reset quirk
Commit7324a7a0d5
("bus: ti-sysc: Implement display subsystem reset quirk") added support for DSS reset, but is using dispc offset also for DSS also registers as reported by Tomi Valkeinen <tomi.valkeinen@ti.com>. Also, we're not using dispc_offset for dispc IRQSTATUS register so let's fix that too. Fixes:7324a7a0d5
("bus: ti-sysc: Implement display subsystem reset quirk") Reported-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
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@ -1566,7 +1566,7 @@ static void sysc_pre_reset_quirk_dss(struct sysc *ddata)
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return;
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/* Clear IRQSTATUS */
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sysc_write(ddata, 0x1000 + 0x18, irq_mask);
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sysc_write(ddata, dispc_offset + 0x18, irq_mask);
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/* Disable outputs */
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val = sysc_quirk_dispc(ddata, dispc_offset, true);
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@ -1580,14 +1580,14 @@ static void sysc_pre_reset_quirk_dss(struct sysc *ddata)
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if (sysc_soc->soc == SOC_3430) {
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/* Clear DSS_SDI_CONTROL */
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sysc_write(ddata, dispc_offset + 0x44, 0);
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sysc_write(ddata, 0x44, 0);
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/* Clear DSS_PLL_CONTROL */
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sysc_write(ddata, dispc_offset + 0x48, 0);
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sysc_write(ddata, 0x48, 0);
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}
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/* Clear DSS_CONTROL to switch DSS clock sources to PRCM if not */
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sysc_write(ddata, dispc_offset + 0x40, 0);
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sysc_write(ddata, 0x40, 0);
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}
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/* 1-wire needs module's internal clocks enabled for reset */
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