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MIPS: Optimize current_cpu_type() for better code. 

o Move current_cpu_type() to a separate header file
 o #ifdefing on supported CPU types lets modern GCC know that certain
   code in callers may be discarded ideally turning current_cpu_type() into
   a function returning a constant.
 o Use current_cpu_type() rather than direct access to struct cpuinfo_mips.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/5833/
hifive-unleashed-5.1
Ralf Baechle 2013-09-17 10:25:47 +02:00
parent ff522058bd
commit 69f24d1784
19 changed files with 236 additions and 19 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
arch/mips/cavium-octeon/csrc-octeon.c
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@ -12,6 +12,7 @@
#include <linux/smp.h>
#include <asm/cpu-info.h>
#include <asm/cpu-type.h>
#include <asm/time.h>
#include <asm/octeon/octeon.h>

1
arch/mips/dec/prom/init.c
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@ -13,6 +13,7 @@
#include <asm/bootinfo.h>
#include <asm/cpu.h>
#include <asm/cpu-type.h>
#include <asm/processor.h>
#include <asm/dec/prom.h>

6
arch/mips/include/asm/cpu-features.h
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@ -13,12 +13,6 @@
#include <asm/cpu-info.h>
#include <cpu-feature-overrides.h>
#ifndef current_cpu_type
#define current_cpu_type() current_cpu_data.cputype
#endif
#define boot_cpu_type() cpu_data[0].cputype
/*
* SMP assumption: Options of CPU 0 are a superset of all processors.
* This is true for all known MIPS systems.

203
arch/mips/include/asm/cpu-type.h 100644
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@ -0,0 +1,203 @@
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2003, 2004 Ralf Baechle
* Copyright (C) 2004 Maciej W. Rozycki
*/
#ifndef __ASM_CPU_TYPE_H
#define __ASM_CPU_TYPE_H
#include <linux/smp.h>
#include <linux/compiler.h>
static inline int __pure __get_cpu_type(const int cpu_type)
{
switch (cpu_type) {
#if defined(CONFIG_SYS_HAS_CPU_LOONGSON2E) || \
defined(CONFIG_SYS_HAS_CPU_LOONGSON2F)
case CPU_LOONGSON2:
#endif
#ifdef CONFIG_SYS_HAS_CPU_LOONGSON1B
case CPU_LOONGSON1:
#endif
#ifdef CONFIG_SYS_HAS_CPU_MIPS32_R1
case CPU_4KC:
case CPU_ALCHEMY:
case CPU_BMIPS3300:
case CPU_BMIPS4350:
case CPU_PR4450:
case CPU_BMIPS32:
case CPU_JZRISC:
#endif
#if defined(CONFIG_SYS_HAS_CPU_MIPS32_R1) || \
defined(CONFIG_SYS_HAS_CPU_MIPS32_R2)
case CPU_4KEC:
#endif
#ifdef CONFIG_SYS_HAS_CPU_MIPS32_R2
case CPU_4KSC:
case CPU_24K:
case CPU_34K:
case CPU_1004K:
case CPU_74K:
case CPU_M14KC:
case CPU_M14KEC:
#endif
#ifdef CONFIG_SYS_HAS_CPU_MIPS64_R1
case CPU_5KC:
case CPU_5KE:
case CPU_20KC:
case CPU_25KF:
case CPU_SB1:
case CPU_SB1A:
#endif
#ifdef CONFIG_SYS_HAS_CPU_MIPS64_R2
/*
* All MIPS64 R2 processors have their own special symbols. That is,
* there currently is no pure R2 core
*/
#endif
#ifdef CONFIG_SYS_HAS_CPU_R3000
case CPU_R2000:
case CPU_R3000:
case CPU_R3000A:
case CPU_R3041:
case CPU_R3051:
case CPU_R3052:
case CPU_R3081:
case CPU_R3081E:
#endif
#ifdef CONFIG_SYS_HAS_CPU_TX39XX
case CPU_TX3912:
case CPU_TX3922:
case CPU_TX3927:
#endif
#ifdef CONFIG_SYS_HAS_CPU_VR41XX
case CPU_VR41XX:
case CPU_VR4111:
case CPU_VR4121:
case CPU_VR4122:
case CPU_VR4131:
case CPU_VR4133:
case CPU_VR4181:
case CPU_VR4181A:
#endif
#ifdef CONFIG_SYS_HAS_CPU_R4300
case CPU_R4300:
case CPU_R4310:
#endif
#ifdef CONFIG_SYS_HAS_CPU_R4X00
case CPU_R4000PC:
case CPU_R4000SC:
case CPU_R4000MC:
case CPU_R4200:
case CPU_R4400PC:
case CPU_R4400SC:
case CPU_R4400MC:
case CPU_R4600:
case CPU_R4700:
case CPU_R4640:
case CPU_R4650:
#endif
#ifdef CONFIG_SYS_HAS_CPU_TX49XX
case CPU_TX49XX:
#endif
#ifdef CONFIG_SYS_HAS_CPU_R5000
case CPU_R5000:
#endif
#ifdef CONFIG_SYS_HAS_CPU_R5432
case CPU_R5432:
#endif
#ifdef CONFIG_SYS_HAS_CPU_R5500
case CPU_R5500:
#endif
#ifdef CONFIG_SYS_HAS_CPU_R6000
case CPU_R6000:
case CPU_R6000A:
#endif
#ifdef CONFIG_SYS_HAS_CPU_NEVADA
case CPU_NEVADA:
#endif
#ifdef CONFIG_SYS_HAS_CPU_R8000
case CPU_R8000:
#endif
#ifdef CONFIG_SYS_HAS_CPU_R10000
case CPU_R10000:
case CPU_R12000:
case CPU_R14000:
#endif
#ifdef CONFIG_SYS_HAS_CPU_RM7000
case CPU_RM7000:
case CPU_SR71000:
#endif
#ifdef CONFIG_SYS_HAS_CPU_RM9000
case CPU_RM9000:
#endif
#ifdef CONFIG_SYS_HAS_CPU_SB1
case CPU_SB1:
case CPU_SB1A:
#endif
#ifdef CONFIG_SYS_HAS_CPU_CAVIUM_OCTEON
case CPU_CAVIUM_OCTEON:
case CPU_CAVIUM_OCTEON_PLUS:
case CPU_CAVIUM_OCTEON2:
#endif
#ifdef CONFIG_SYS_HAS_CPU_BMIPS4380
case CPU_BMIPS4380:
#endif
#ifdef CONFIG_SYS_HAS_CPU_BMIPS5000
case CPU_BMIPS5000:
#endif
#ifdef CONFIG_SYS_HAS_CPU_XLP
case CPU_XLP:
#endif
#ifdef CONFIG_SYS_HAS_CPU_XLR
case CPU_XLR:
#endif
break;
default:
unreachable();
}
return cpu_type;
}
static inline int __pure current_cpu_type(void)
{
const int cpu_type = current_cpu_data.cputype;
return __get_cpu_type(cpu_type);
}
static inline int __pure boot_cpu_type(void)
{
const int cpu_type = cpu_data[0].cputype;
return __get_cpu_type(cpu_type);
}
#endif /* __ASM_CPU_TYPE_H */

2
arch/mips/include/asm/mach-ip22/cpu-feature-overrides.h
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@ -8,6 +8,8 @@
#ifndef __ASM_MACH_IP22_CPU_FEATURE_OVERRIDES_H
#define __ASM_MACH_IP22_CPU_FEATURE_OVERRIDES_H
#include <asm/cpu.h>
/*
* IP22 with a variety of processors so we can't use defaults for everything.
*/

2
arch/mips/include/asm/mach-ip27/cpu-feature-overrides.h
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@ -8,6 +8,8 @@
#ifndef __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H
#define __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H
#include <asm/cpu.h>
/*
* IP27 only comes with R10000 family processors all using the same config
*/

2
arch/mips/include/asm/mach-ip28/cpu-feature-overrides.h
View File

@ -9,6 +9,8 @@
#ifndef __ASM_MACH_IP28_CPU_FEATURE_OVERRIDES_H
#define __ASM_MACH_IP28_CPU_FEATURE_OVERRIDES_H
#include <asm/cpu.h>
/*
* IP28 only comes with R10000 family processors all using the same config
*/

3
arch/mips/kernel/cpu-probe.c
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@ -20,6 +20,7 @@
#include <asm/bugs.h>
#include <asm/cpu.h>
#include <asm/cpu-type.h>
#include <asm/fpu.h>
#include <asm/mipsregs.h>
#include <asm/watch.h>
@ -55,7 +56,7 @@ static inline void check_errata(void)
{
struct cpuinfo_mips *c = &current_cpu_data;
switch (c->cputype) {
switch (current_cpu_type()) {
case CPU_34K:
/*
* Erratum "RPS May Cause Incorrect Instruction Execution"

3
arch/mips/kernel/idle.c
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@ -18,6 +18,7 @@
#include <linux/sched.h>
#include <asm/cpu.h>
#include <asm/cpu-info.h>
#include <asm/cpu-type.h>
#include <asm/idle.h>
#include <asm/mipsregs.h>
@ -136,7 +137,7 @@ void __init check_wait(void)
return;
}
switch (c->cputype) {
switch (current_cpu_type()) {
case CPU_R3081:
case CPU_R3081E:
cpu_wait = r3081_wait;

1
arch/mips/kernel/time.c
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@ -24,6 +24,7 @@
#include <linux/export.h>
#include <asm/cpu-features.h>
#include <asm/cpu-type.h>
#include <asm/div64.h>
#include <asm/smtc_ipi.h>
#include <asm/time.h>

3
arch/mips/kernel/traps.c
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@ -39,6 +39,7 @@
#include <asm/break.h>
#include <asm/cop2.h>
#include <asm/cpu.h>
#include <asm/cpu-type.h>
#include <asm/dsp.h>
#include <asm/fpu.h>
#include <asm/fpu_emulator.h>
@ -622,7 +623,7 @@ static int simulate_rdhwr(struct pt_regs *regs, int rd, int rt)
regs->regs[rt] = read_c0_count();
return 0;
case 3: /* Count register resolution */
switch (current_cpu_data.cputype) {
switch (current_cpu_type()) {
case CPU_20KC:
case CPU_25KF:
regs->regs[rt] = 1;

6
arch/mips/mm/c-octeon.c
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@ -19,6 +19,7 @@
#include <asm/bootinfo.h>
#include <asm/cacheops.h>
#include <asm/cpu-features.h>
#include <asm/cpu-type.h>
#include <asm/page.h>
#include <asm/pgtable.h>
#include <asm/r4kcache.h>
@ -186,9 +187,10 @@ static void probe_octeon(void)
unsigned long dcache_size;
unsigned int config1;
struct cpuinfo_mips *c = &current_cpu_data;
int cputype = current_cpu_type();
config1 = read_c0_config1();
switch (c->cputype) {
switch (cputype) {
case CPU_CAVIUM_OCTEON:
case CPU_CAVIUM_OCTEON_PLUS:
c->icache.linesz = 2 << ((config1 >> 19) & 7);
@ -199,7 +201,7 @@ static void probe_octeon(void)
c->icache.sets * c->icache.ways * c->icache.linesz;
c->icache.waybit = ffs(icache_size / c->icache.ways) - 1;
c->dcache.linesz = 128;
if (c->cputype == CPU_CAVIUM_OCTEON_PLUS)
if (cputype == CPU_CAVIUM_OCTEON_PLUS)
c->dcache.sets = 2; /* CN5XXX has two Dcache sets */
else
c->dcache.sets = 1; /* CN3XXX has one Dcache set */

14
arch/mips/mm/c-r4k.c
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@ -25,6 +25,7 @@
#include <asm/cacheops.h>
#include <asm/cpu.h>
#include <asm/cpu-features.h>
#include <asm/cpu-type.h>
#include <asm/io.h>
#include <asm/page.h>
#include <asm/pgtable.h>
@ -814,7 +815,7 @@ static void probe_pcache(void)
unsigned long config1;
unsigned int lsize;
switch (c->cputype) {
switch (current_cpu_type()) {
case CPU_R4600: /* QED style two way caches? */
case CPU_R4700:
case CPU_R5000:
@ -1050,7 +1051,7 @@ static void probe_pcache(void)
* normally they'd suffer from aliases but magic in the hardware deals
* with that for us so we don't need to take care ourselves.
*/
switch (c->cputype) {
switch (current_cpu_type()) {
case CPU_20KC:
case CPU_25KF:
case CPU_SB1:
@ -1070,7 +1071,7 @@ static void probe_pcache(void)
case CPU_34K:
case CPU_74K:
case CPU_1004K:
if (c->cputype == CPU_74K)
if (current_cpu_type() == CPU_74K)
alias_74k_erratum(c);
if ((read_c0_config7() & (1 << 16))) {
/* effectively physically indexed dcache,
@ -1083,7 +1084,7 @@ static void probe_pcache(void)
c->dcache.flags |= MIPS_CACHE_ALIASES;
}
switch (c->cputype) {
switch (current_cpu_type()) {
case CPU_20KC:
/*
* Some older 20Kc chips doesn't have the 'VI' bit in
@ -1212,7 +1213,7 @@ static void setup_scache(void)
* processors don't have a S-cache that would be relevant to the
* Linux memory management.
*/
switch (c->cputype) {
switch (current_cpu_type()) {
case CPU_R4000SC:
case CPU_R4000MC:
case CPU_R4400SC:
@ -1389,9 +1390,8 @@ static void r4k_cache_error_setup(void)
{
extern char __weak except_vec2_generic;
extern char __weak except_vec2_sb1;
struct cpuinfo_mips *c = &current_cpu_data;
switch (c->cputype) {
switch (current_cpu_type()) {
case CPU_SB1:
case CPU_SB1A:
set_uncached_handler(0x100, &except_vec2_sb1, 0x80);

1
arch/mips/mm/dma-default.c
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@ -18,6 +18,7 @@
#include <linux/highmem.h>
#include <asm/cache.h>
#include <asm/cpu-type.h>
#include <asm/io.h>
#include <dma-coherence.h>

1
arch/mips/mm/page.c
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@ -18,6 +18,7 @@
#include <asm/bugs.h>
#include <asm/cacheops.h>
#include <asm/cpu-type.h>
#include <asm/inst.h>
#include <asm/io.h>
#include <asm/page.h>

3
arch/mips/mm/sc-mips.c
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@ -6,6 +6,7 @@
#include <linux/sched.h>
#include <linux/mm.h>
#include <asm/cpu-type.h>
#include <asm/mipsregs.h>
#include <asm/bcache.h>
#include <asm/cacheops.h>
@ -71,7 +72,7 @@ static inline int mips_sc_is_activated(struct cpuinfo_mips *c)
unsigned int tmp;
/* Check the bypass bit (L2B) */
switch (c->cputype) {
switch (current_cpu_type()) {
case CPU_34K:
case CPU_74K:
case CPU_1004K:

1
arch/mips/mm/tlb-r4k.c
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@ -16,6 +16,7 @@
#include <linux/module.h>
#include <asm/cpu.h>
#include <asm/cpu-type.h>
#include <asm/bootinfo.h>
#include <asm/mmu_context.h>
#include <asm/pgtable.h>

1
arch/mips/mm/tlbex.c
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@ -30,6 +30,7 @@
#include <linux/cache.h>
#include <asm/cacheflush.h>
#include <asm/cpu-type.h>
#include <asm/pgtable.h>
#include <asm/war.h>
#include <asm/uasm.h>

1
arch/mips/oprofile/common.c
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@ -12,6 +12,7 @@
#include <linux/oprofile.h>
#include <linux/smp.h>
#include <asm/cpu-info.h>
#include <asm/cpu-type.h>
#include "op_impl.h"