Renesas ARM Based SoC Updates for v4.14
* Add debug-ll support to RZ/G1M (r8a7743) SoC Chris Paterson says, "RZ/G1M uses SCIF0 for the debug console, like most of the R-Car Gen2 SoCs." * Remove ARCH_SHMOBILE_MULTI Geert Uytterhoeven says, "The migration from ARCH_SHMOBILE_MULTI to ARCH_RENESAS has been completed in v4.12..." * Correct arch timer frequency on RZ/G1M (r8a7743) SoC Geert Uytterhoeven says, "According to the datasheet, the frequency of the ARM architecture timer on RZ/G1E depends on the frequency of the ZS clock..." * Add support for CPG/MSSR bindings Geert Uytterhoeven says, "When using the new CPG/MSSR bindings, there is no longer a "renesas,rcar-gen2-cpg-clocks" node, and the code to obtain the external clock crystal frequency falls back to a default of 20 MHz. While this is correct for all upstream R-Car Gen2 and RZ/G1 boards, this is not necessarily the case for out-of-tree third party boards. Add support for finding the external clock crystal oscillator on RZ/G1M, and on R-Car H2, M2-W, and M2-N using the new CPG/MSSR bindings, through the corresponding "renesas,r8a77xx-cpg-mssr" nodes." * Obtain jump stub region from DT Geert Uytterhoeven says, "Add support for obtaining from DT the SRAM region to store the jump stub for CPU core bringup, according to the renesas,smp-sram DT bindings." -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJZf0J3AAoJENfPZGlqN0++GfAP/21nuyREfKfOBV2B3DOAXVWS VhqOSgOaK/oAVfIfk7dSrk+ZqRF0fgF14EDQyzaNgi/coPb0cL2Xt8fpbYIp/H1/ BBjJg/Q+XptMRWGbh4oshgO2W4wNCXyPJRQ/x7ciDFkygJqgmbu0sF1CF6spis/K n3sDS4w/bJVOnTZhOG6v0U0p80X0nc0W4M8fQPZjhecBjPCXGmqOekH7Tm9HmJgu HktXX8OsngGMfI9NUPQcl8KgPWNfBi4U0X4Ep5cTGutJ25WsQiW4LDoSFFrF1JIY Kll985IvAgLfAOEeezrua+/cM1FsOOZBQyXmV9awBmLEmzicyxOr7Lp1eK3RfADw RQ2foFnUYakMfJcnVVjZD8tNg+eNafN0VjSwbvlvQH+1P+vy5EvUKovjyed7u9n9 TIuewlrrJdMAMx2wwFEeotzU3JjZB0rIJb0hzy9zk/qekC0II4O25Y1gH16tfYJa 65UC172dQmjt3mP7aK88V0bJX5NNKU7/1YALHplih3qRuqov2CgCUtdEdzqHJgYh C4Thd1ejdFTgWSqaBUInQfBs3lNDO1JfwfdVCmLq7tG8jEpV/zZTeywxqizMEIsH 6f/cd7oTkIbZ9i2UVOMnhWQhyGIkOJD+/ylr4D7iqhL0yC7/mCcalHR8FsNps81J qA4Hy70ALb/D8A9PMjgE =PJul -----END PGP SIGNATURE----- Merge tag 'renesas-soc-for-v4.14' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc Pull "Renesas ARM Based SoC Updates for v4.14" Simon Horman: * Add debug-ll support to RZ/G1M (r8a7743) SoC Chris Paterson says, "RZ/G1M uses SCIF0 for the debug console, like most of the R-Car Gen2 SoCs." * Remove ARCH_SHMOBILE_MULTI Geert Uytterhoeven says, "The migration from ARCH_SHMOBILE_MULTI to ARCH_RENESAS has been completed in v4.12..." * Correct arch timer frequency on RZ/G1M (r8a7743) SoC Geert Uytterhoeven says, "According to the datasheet, the frequency of the ARM architecture timer on RZ/G1E depends on the frequency of the ZS clock..." * Add support for CPG/MSSR bindings Geert Uytterhoeven says, "When using the new CPG/MSSR bindings, there is no longer a "renesas,rcar-gen2-cpg-clocks" node, and the code to obtain the external clock crystal frequency falls back to a default of 20 MHz. While this is correct for all upstream R-Car Gen2 and RZ/G1 boards, this is not necessarily the case for out-of-tree third party boards. Add support for finding the external clock crystal oscillator on RZ/G1M, and on R-Car H2, M2-W, and M2-N using the new CPG/MSSR bindings, through the corresponding "renesas,r8a77xx-cpg-mssr" nodes." * Obtain jump stub region from DT Geert Uytterhoeven says, "Add support for obtaining from DT the SRAM region to store the jump stub for CPU core bringup, according to the renesas,smp-sram DT bindings." * tag 'renesas-soc-for-v4.14' of https://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: Remove ARCH_SHMOBILE_MULTI ARM: shmobile: rcar-gen2: Correct arch timer frequency on RZ/G1E ARM: shmobile: rcar-gen2: Add support for CPG/MSSR bindings ARM: shmobile: rcar-gen2: Obtain jump stub region from DT ARM: debug-ll: Add support for r8a7743
This commit is contained in:
Arnd Bergmann
commit
6a1aa09b15
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@ -896,12 +896,13 @@ choice
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via SCIF2 on Renesas R-Car H1 (R8A7779).
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config DEBUG_RCAR_GEN2_SCIF0
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bool "Kernel low-level debugging messages via SCIF0 on R8A7790/R8A7791/R8A7792/R8A7793"
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depends on ARCH_R8A7790 || ARCH_R8A7791 || ARCH_R8A7792 || ARCH_R8A7793
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bool "Kernel low-level debugging messages via SCIF0 on R-Car Gen2 and RZ/G1"
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depends on ARCH_R8A7743 || ARCH_R8A7790 || ARCH_R8A7791 || \
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ARCH_R8A7792 || ARCH_R8A7793
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help
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Say Y here if you want kernel low-level debugging support
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via SCIF0 on Renesas R-Car H2 (R8A7790), M2-W (R8A7791), V2H
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(R8A7792), or M2-N (R8A7793).
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via SCIF0 on Renesas RZ/G1M (R8A7743), R-Car H2 (R8A7790),
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M2-W (R8A7791), V2H (R8A7792), or M2-N (R8A7793).
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config DEBUG_RCAR_GEN2_SCIF2
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bool "Kernel low-level debugging messages via SCIF2 on R8A7794"
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@ -1,9 +1,6 @@
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config ARCH_SHMOBILE
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bool
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config ARCH_SHMOBILE_MULTI
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bool
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config PM_RMOBILE
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bool
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select PM
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@ -34,7 +31,6 @@ menuconfig ARCH_RENESAS
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depends on ARCH_MULTI_V7 && MMU
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select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
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select ARCH_SHMOBILE
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select ARCH_SHMOBILE_MULTI
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select ARM_GIC
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select GPIOLIB
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select HAVE_ARM_SCU if SMP
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@ -11,7 +11,9 @@
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*/
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#include <linux/kernel.h>
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#include <linux/ioport.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/smp.h>
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#include <linux/soc/renesas/rcar-sysc.h>
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#include <asm/io.h>
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@ -69,8 +71,9 @@ void __init rcar_gen2_pm_init(void)
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struct device_node *np, *cpus;
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bool has_a7 = false;
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bool has_a15 = false;
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phys_addr_t boot_vector_addr = ICRAM1;
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struct resource res;
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u32 syscier = 0;
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int error;
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if (once++)
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return;
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@ -91,14 +94,38 @@ void __init rcar_gen2_pm_init(void)
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else if (of_machine_is_compatible("renesas,r8a7791"))
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syscier = 0x00111003;
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np = of_find_compatible_node(NULL, NULL, "renesas,smp-sram");
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if (!np) {
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/* No smp-sram in DT, fall back to hardcoded address */
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res = (struct resource)DEFINE_RES_MEM(ICRAM1,
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shmobile_boot_size);
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goto map;
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}
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error = of_address_to_resource(np, 0, &res);
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if (error) {
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pr_err("Failed to get smp-sram address: %d\n", error);
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return;
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}
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map:
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/* RAM for jump stub, because BAR requires 256KB aligned address */
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p = ioremap_nocache(boot_vector_addr, shmobile_boot_size);
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if (res.start & (256 * 1024 - 1) ||
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resource_size(&res) < shmobile_boot_size) {
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pr_err("Invalid smp-sram region\n");
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return;
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}
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p = ioremap(res.start, resource_size(&res));
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if (!p)
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return;
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memcpy_toio(p, shmobile_boot_vector, shmobile_boot_size);
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iounmap(p);
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/* setup reset vectors */
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p = ioremap_nocache(RST, 0x63);
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bar = phys_to_sbar(boot_vector_addr);
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bar = phys_to_sbar(res.start);
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if (has_a15) {
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writel_relaxed(bar, p + CA15BAR);
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writel_relaxed(bar | SBAR_BAREN, p + CA15BAR);
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@ -29,17 +29,29 @@
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#include "common.h"
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#include "rcar-gen2.h"
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static const struct of_device_id cpg_matches[] __initconst = {
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{ .compatible = "renesas,rcar-gen2-cpg-clocks", },
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{ .compatible = "renesas,r8a7743-cpg-mssr", .data = "extal" },
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{ .compatible = "renesas,r8a7790-cpg-mssr", .data = "extal" },
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{ .compatible = "renesas,r8a7791-cpg-mssr", .data = "extal" },
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{ .compatible = "renesas,r8a7793-cpg-mssr", .data = "extal" },
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{ /* sentinel */ }
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};
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static unsigned int __init get_extal_freq(void)
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{
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const struct of_device_id *match;
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struct device_node *cpg, *extal;
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u32 freq = 20000000;
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int idx = 0;
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cpg = of_find_compatible_node(NULL, NULL,
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"renesas,rcar-gen2-cpg-clocks");
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cpg = of_find_matching_node_and_match(NULL, cpg_matches, &match);
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if (!cpg)
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return freq;
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extal = of_parse_phandle(cpg, "clocks", 0);
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if (match->data)
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idx = of_property_match_string(cpg, "clock-names", match->data);
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extal = of_parse_phandle(cpg, "clocks", idx);
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of_node_put(cpg);
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if (!extal)
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return freq;
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@ -58,7 +70,8 @@ void __init rcar_gen2_timer_init(void)
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void __iomem *base;
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u32 freq;
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if (of_machine_is_compatible("renesas,r8a7792") ||
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if (of_machine_is_compatible("renesas,r8a7745") ||
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of_machine_is_compatible("renesas,r8a7792") ||
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of_machine_is_compatible("renesas,r8a7794")) {
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freq = 260000000 / 8; /* ZS / 8 */
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/* CNTVOFF has to be initialized either from non-secure
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