parisc: fix partly 16/64k PAGE_SIZE boot
This patch fixes partly PAGE_SIZEs of 16K or 64K by adjusting the assembler PTE lookup code and the assembler TEMPALIAS code. Furthermore some data alignments for PAGE_SIZE have been limited to 4K (or less) to not waste too much memory with greater page sizes. As a side note, the palo loader can (currently) only handle up to 10 ELF segments which is fixed with tighter aligning as well. My testings indicated that the ldci command in the sba iommu coding needed adjustment by the PAGE_SHIFT value and that the I/O PDIR Page size was only set to 4K for my machine (C3000). All this fixes partly the boot, but there are still quite some caching problems left. Examples are e.g. the symbios logic driver which is failing: sym0: <896> rev 0x7 at pci 0000:00:0f.0 irq 69 sym0: PA-RISC Firmware, ID 7, Fast-40, SE, parity checking CACHE TEST FAILED: DMA error (dstat=0x81).sym0: CACHE INCORRECTLY CONFIGURED. and the tulip network driver which doesn't seem to work correctly either: Sending BOOTP requests .net eth0: Setting full-duplex based on MII#1 link partner capability of 05e1 ..... timed out! Beside those kernel fixes glibc will need fixes too to be able to handle >4K page sizes. Signed-off-by: Helge Deller <deller@gmx.de>hifive-unleashed-5.1
Helge Deller
parent
7f64fb41aa
commit
6a45716abb
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@ -400,7 +400,15 @@
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#if PT_NLEVELS == 3
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extru \va,31-ASM_PMD_SHIFT,ASM_BITS_PER_PMD,\index
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#else
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# if defined(CONFIG_64BIT)
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extrd,u \va,63-ASM_PGDIR_SHIFT,ASM_BITS_PER_PGD,\index
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#else
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# if PAGE_SIZE > 4096
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extru \va,31-ASM_PGDIR_SHIFT,32-ASM_PGDIR_SHIFT,\index
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# else
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extru \va,31-ASM_PGDIR_SHIFT,ASM_BITS_PER_PGD,\index
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# endif
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# endif
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#endif
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dep %r0,31,PAGE_SHIFT,\pmd /* clear offset */
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copy %r0,\pte
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@ -615,7 +623,7 @@
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.text
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.align PAGE_SIZE
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.align 4096
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ENTRY(fault_vector_20)
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/* First vector is invalid (0) */
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@ -55,13 +55,13 @@
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* IODC requires 7K byte stack. That leaves 1K byte for os_hpmc.
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*/
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.align PAGE_SIZE
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.align 4096
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hpmc_stack:
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.block 16384
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#define HPMC_IODC_BUF_SIZE 0x8000
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.align PAGE_SIZE
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.align 4096
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hpmc_iodc_buf:
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.block HPMC_IODC_BUF_SIZE
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@ -563,6 +563,15 @@ ENDPROC(copy_page_asm)
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* %r23 physical page (shifted for tlb insert) of "from" translation
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*/
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/* Drop prot bits and convert to page addr for iitlbt and idtlbt */
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#define PAGE_ADD_SHIFT (PAGE_SHIFT-12)
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.macro convert_phys_for_tlb_insert20 phys
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extrd,u \phys, 56-PAGE_ADD_SHIFT, 32-PAGE_ADD_SHIFT, \phys
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#if _PAGE_SIZE_ENCODING_DEFAULT
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depdi _PAGE_SIZE_ENCODING_DEFAULT, 63, (63-58), \phys
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#endif
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.endm
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/*
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* We can't do this since copy_user_page is used to bring in
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* file data that might have instructions. Since the data would
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@ -589,15 +598,14 @@ ENTRY(copy_user_page_asm)
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sub %r25, %r1, %r23
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ldil L%(TMPALIAS_MAP_START), %r28
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/* FIXME for different page sizes != 4k */
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#ifdef CONFIG_64BIT
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#if (TMPALIAS_MAP_START >= 0x80000000)
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depdi 0, 31,32, %r28 /* clear any sign extension */
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#endif
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extrd,u %r26,56,32, %r26 /* convert phys addr to tlb insert format */
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extrd,u %r23,56,32, %r23 /* convert phys addr to tlb insert format */
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convert_phys_for_tlb_insert20 %r26 /* convert phys addr to tlb insert format */
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convert_phys_for_tlb_insert20 %r23 /* convert phys addr to tlb insert format */
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depd %r24,63,22, %r28 /* Form aliased virtual address 'to' */
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depdi 0, 63,12, %r28 /* Clear any offset bits */
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depdi 0, 63,PAGE_SHIFT, %r28 /* Clear any offset bits */
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copy %r28, %r29
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depdi 1, 41,1, %r29 /* Form aliased virtual address 'from' */
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#else
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@ -747,11 +755,10 @@ ENTRY(clear_user_page_asm)
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#ifdef CONFIG_64BIT
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#if (TMPALIAS_MAP_START >= 0x80000000)
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depdi 0, 31,32, %r28 /* clear any sign extension */
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/* FIXME: page size dependend */
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#endif
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extrd,u %r26, 56,32, %r26 /* convert phys addr to tlb insert format */
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convert_phys_for_tlb_insert20 %r26 /* convert phys addr to tlb insert format */
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depd %r25, 63,22, %r28 /* Form aliased virtual address 'to' */
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depdi 0, 63,12, %r28 /* Clear any offset bits */
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depdi 0, 63,PAGE_SHIFT, %r28 /* Clear any offset bits */
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#else
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extrw,u %r26, 24,25, %r26 /* convert phys addr to tlb insert format */
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depw %r25, 31,22, %r28 /* Form aliased virtual address 'to' */
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@ -832,11 +839,10 @@ ENTRY(flush_dcache_page_asm)
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#ifdef CONFIG_64BIT
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#if (TMPALIAS_MAP_START >= 0x80000000)
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depdi 0, 31,32, %r28 /* clear any sign extension */
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/* FIXME: page size dependend */
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#endif
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extrd,u %r26, 56,32, %r26 /* convert phys addr to tlb insert format */
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convert_phys_for_tlb_insert20 %r26 /* convert phys addr to tlb insert format */
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depd %r25, 63,22, %r28 /* Form aliased virtual address 'to' */
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depdi 0, 63,12, %r28 /* Clear any offset bits */
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depdi 0, 63,PAGE_SHIFT, %r28 /* Clear any offset bits */
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#else
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extrw,u %r26, 24,25, %r26 /* convert phys addr to tlb insert format */
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depw %r25, 31,22, %r28 /* Form aliased virtual address 'to' */
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@ -909,11 +915,10 @@ ENTRY(flush_icache_page_asm)
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#ifdef CONFIG_64BIT
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#if (TMPALIAS_MAP_START >= 0x80000000)
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depdi 0, 31,32, %r28 /* clear any sign extension */
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/* FIXME: page size dependend */
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#endif
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extrd,u %r26, 56,32, %r26 /* convert phys addr to tlb insert format */
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convert_phys_for_tlb_insert20 %r26 /* convert phys addr to tlb insert format */
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depd %r25, 63,22, %r28 /* Form aliased virtual address 'to' */
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depdi 0, 63,12, %r28 /* Clear any offset bits */
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depdi 0, 63,PAGE_SHIFT, %r28 /* Clear any offset bits */
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#else
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extrw,u %r26, 24,25, %r26 /* convert phys addr to tlb insert format */
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depw %r25, 31,22, %r28 /* Form aliased virtual address 'to' */
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@ -959,7 +964,7 @@ ENTRY(flush_icache_page_asm)
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fic,m %r1(%sr4,%r28)
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fic,m %r1(%sr4,%r28)
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fic,m %r1(%sr4,%r28)
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cmpb,COND(<<) %r28, %r25,1b
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cmpb,COND(<<) %r28, %r25,1b
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fic,m %r1(%sr4,%r28)
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sync
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@ -129,6 +129,8 @@ void __init setup_arch(char **cmdline_p)
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printk(KERN_INFO "The 32-bit Kernel has started...\n");
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#endif
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printk(KERN_INFO "Default page size is %dKB.\n", (int)(PAGE_SIZE / 1024));
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pdc_console_init();
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#ifdef CONFIG_64BIT
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@ -15,6 +15,7 @@
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#include <asm/thread_info.h>
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#include <asm/assembly.h>
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#include <asm/processor.h>
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#include <asm/cache.h>
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#include <linux/linkage.h>
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@ -643,7 +644,7 @@ ENTRY(end_linux_gateway_page)
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.section .rodata,"a"
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.align PAGE_SIZE
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.align 8
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/* Light-weight-syscall table */
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/* Start of lws table. */
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ENTRY(lws_table)
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@ -652,13 +653,13 @@ ENTRY(lws_table)
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END(lws_table)
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/* End of lws table */
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.align PAGE_SIZE
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.align 8
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ENTRY(sys_call_table)
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#include "syscall_table.S"
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END(sys_call_table)
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#ifdef CONFIG_64BIT
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.align PAGE_SIZE
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.align 8
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ENTRY(sys_call_table64)
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#define SYSCALL_TABLE_64BIT
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#include "syscall_table.S"
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@ -674,7 +675,7 @@ END(sys_call_table64)
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with ldcw.
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*/
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.section .data
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.align PAGE_SIZE
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.align L1_CACHE_BYTES
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ENTRY(lws_lock_start)
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/* lws locks */
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.rept 16
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@ -575,7 +575,7 @@ sba_io_pdir_entry(u64 *pdir_ptr, space_t sid, unsigned long vba,
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mtsp(sid,1);
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asm("lci 0(%%sr1, %1), %0" : "=r" (ci) : "r" (vba));
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pa |= (ci >> 12) & 0xff; /* move CI (8 bits) into lowest byte */
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pa |= (ci >> PAGE_SHIFT) & 0xff; /* move CI (8 bits) into lowest byte */
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pa |= SBA_PDIR_VALID_BIT; /* set "valid" bit */
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*pdir_ptr = cpu_to_le64(pa); /* swap and store into I/O Pdir */
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@ -1376,7 +1376,7 @@ static void
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sba_ioc_init(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
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{
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u32 iova_space_size, iova_space_mask;
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unsigned int pdir_size, iov_order;
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unsigned int pdir_size, iov_order, tcnfg;
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/*
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** Determine IOVA Space size from memory size.
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@ -1468,8 +1468,19 @@ sba_ioc_init(struct parisc_device *sba, struct ioc *ioc, int ioc_num)
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WRITE_REG(ioc->ibase | 1, ioc->ioc_hpa+IOC_IBASE);
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WRITE_REG(ioc->imask, ioc->ioc_hpa+IOC_IMASK);
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/* Set I/O PDIR Page size to 4K */
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WRITE_REG(0, ioc->ioc_hpa+IOC_TCNFG);
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/* Set I/O PDIR Page size to system page size */
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switch (PAGE_SHIFT) {
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case 12: tcnfg = 0; break; /* 4K */
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case 13: tcnfg = 1; break; /* 8K */
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case 14: tcnfg = 2; break; /* 16K */
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case 16: tcnfg = 3; break; /* 64K */
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default:
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panic(__FILE__ "Unsupported system page size %d",
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1 << PAGE_SHIFT);
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break;
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}
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/* Set I/O PDIR Page size to PAGE_SIZE (4k/16k/...) */
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WRITE_REG(tcnfg, ioc->ioc_hpa+IOC_TCNFG);
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/*
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** Clear I/O TLB of any possible entries.
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