perf/x86: Uncore filter support for SandyBridge-EP
This patch adds C-Box and PCU filter support for SandyBridge-EP uncore. We can filter C-Box events by thread/core ID and filter PCU events by frequency/voltage. Signed-off-by: Yan, Zheng <zheng.z.yan@intel.com> Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Link: http://lkml.kernel.org/r/1341381616-12229-5-git-send-email-zheng.z.yan@intel.com Signed-off-by: Ingo Molnar <mingo@kernel.org>hifive-unleashed-5.1
Yan, Zheng
Ingo Molnar
parent
4208969724
commit
6a67943a18
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@ -14,10 +14,13 @@ static cpumask_t uncore_cpu_mask;
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/* constraint for the fixed counter */
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static struct event_constraint constraint_fixed =
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EVENT_CONSTRAINT(~0ULL, 1 << UNCORE_PMC_IDX_FIXED, ~0ULL);
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static struct event_constraint constraint_empty =
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EVENT_CONSTRAINT(0, 0, 0);
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DEFINE_UNCORE_FORMAT_ATTR(event, event, "config:0-7");
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DEFINE_UNCORE_FORMAT_ATTR(umask, umask, "config:8-15");
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DEFINE_UNCORE_FORMAT_ATTR(edge, edge, "config:18");
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DEFINE_UNCORE_FORMAT_ATTR(tid_en, tid_en, "config:19");
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DEFINE_UNCORE_FORMAT_ATTR(inv, inv, "config:23");
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DEFINE_UNCORE_FORMAT_ATTR(cmask5, cmask, "config:24-28");
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DEFINE_UNCORE_FORMAT_ATTR(cmask8, cmask, "config:24-31");
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@ -26,8 +29,19 @@ DEFINE_UNCORE_FORMAT_ATTR(thresh5, thresh, "config:24-28");
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DEFINE_UNCORE_FORMAT_ATTR(occ_sel, occ_sel, "config:14-15");
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DEFINE_UNCORE_FORMAT_ATTR(occ_invert, occ_invert, "config:30");
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DEFINE_UNCORE_FORMAT_ATTR(occ_edge, occ_edge, "config:14-51");
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DEFINE_UNCORE_FORMAT_ATTR(filter_tid, filter_tid, "config1:0-4");
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DEFINE_UNCORE_FORMAT_ATTR(filter_nid, filter_nid, "config1:10-17");
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DEFINE_UNCORE_FORMAT_ATTR(filter_state, filter_state, "config1:18-22");
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DEFINE_UNCORE_FORMAT_ATTR(filter_opc, filter_opc, "config1:23-31");
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DEFINE_UNCORE_FORMAT_ATTR(filter_brand0, filter_brand0, "config1:0-7");
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DEFINE_UNCORE_FORMAT_ATTR(filter_brand1, filter_brand1, "config1:8-15");
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DEFINE_UNCORE_FORMAT_ATTR(filter_brand2, filter_brand2, "config1:16-23");
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DEFINE_UNCORE_FORMAT_ATTR(filter_brand3, filter_brand3, "config1:24-31");
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/* Sandy Bridge-EP uncore support */
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static struct intel_uncore_type snbep_uncore_cbox;
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static struct intel_uncore_type snbep_uncore_pcu;
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static void snbep_uncore_pci_disable_box(struct intel_uncore_box *box)
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{
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struct pci_dev *pdev = box->pci_dev;
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@ -120,6 +134,10 @@ static void snbep_uncore_msr_enable_event(struct intel_uncore_box *box,
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struct perf_event *event)
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{
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struct hw_perf_event *hwc = &event->hw;
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struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
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if (reg1->idx != EXTRA_REG_NONE)
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wrmsrl(reg1->reg, reg1->config);
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wrmsrl(hwc->config_base, hwc->config | SNBEP_PMON_CTL_EN);
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}
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@ -149,6 +167,71 @@ static void snbep_uncore_msr_init_box(struct intel_uncore_box *box)
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wrmsrl(msr, SNBEP_PMON_BOX_CTL_INT);
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}
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static struct event_constraint *
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snbep_uncore_get_constraint(struct intel_uncore_box *box,
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struct perf_event *event)
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{
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struct intel_uncore_extra_reg *er;
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struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
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unsigned long flags;
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bool ok = false;
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if (reg1->idx == EXTRA_REG_NONE || (box->phys_id >= 0 && reg1->alloc))
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return NULL;
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er = &box->shared_regs[reg1->idx];
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raw_spin_lock_irqsave(&er->lock, flags);
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if (!atomic_read(&er->ref) || er->config1 == reg1->config) {
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atomic_inc(&er->ref);
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er->config1 = reg1->config;
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ok = true;
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}
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raw_spin_unlock_irqrestore(&er->lock, flags);
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if (ok) {
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if (box->phys_id >= 0)
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reg1->alloc = 1;
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return NULL;
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}
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return &constraint_empty;
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}
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static void snbep_uncore_put_constraint(struct intel_uncore_box *box,
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struct perf_event *event)
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{
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struct intel_uncore_extra_reg *er;
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struct hw_perf_event_extra *reg1 = &event->hw.extra_reg;
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if (box->phys_id < 0 || !reg1->alloc)
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return;
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er = &box->shared_regs[reg1->idx];
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atomic_dec(&er->ref);
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reg1->alloc = 0;
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}
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static int snbep_uncore_hw_config(struct intel_uncore_box *box,
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struct perf_event *event)
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{
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struct hw_perf_event *hwc = &event->hw;
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struct hw_perf_event_extra *reg1 = &hwc->extra_reg;
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if (box->pmu->type == &snbep_uncore_cbox) {
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reg1->reg = SNBEP_C0_MSR_PMON_BOX_FILTER +
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SNBEP_CBO_MSR_OFFSET * box->pmu->pmu_idx;
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reg1->config = event->attr.config1 &
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SNBEP_CB0_MSR_PMON_BOX_FILTER_MASK;
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} else if (box->pmu->type == &snbep_uncore_pcu) {
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reg1->reg = SNBEP_PCU_MSR_PMON_BOX_FILTER;
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reg1->config = event->attr.config1 &
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SNBEP_PCU_MSR_PMON_BOX_FILTER_MASK;
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} else {
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return 0;
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}
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reg1->idx = 0;
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return 0;
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}
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static struct attribute *snbep_uncore_formats_attr[] = {
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&format_attr_event.attr,
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&format_attr_umask.attr,
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@ -167,6 +250,20 @@ static struct attribute *snbep_uncore_ubox_formats_attr[] = {
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NULL,
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};
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static struct attribute *snbep_uncore_cbox_formats_attr[] = {
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&format_attr_event.attr,
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&format_attr_umask.attr,
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&format_attr_edge.attr,
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&format_attr_tid_en.attr,
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&format_attr_inv.attr,
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&format_attr_thresh8.attr,
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&format_attr_filter_tid.attr,
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&format_attr_filter_nid.attr,
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&format_attr_filter_state.attr,
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&format_attr_filter_opc.attr,
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NULL,
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};
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static struct attribute *snbep_uncore_pcu_formats_attr[] = {
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&format_attr_event.attr,
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&format_attr_occ_sel.attr,
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@ -175,6 +272,10 @@ static struct attribute *snbep_uncore_pcu_formats_attr[] = {
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&format_attr_thresh5.attr,
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&format_attr_occ_invert.attr,
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&format_attr_occ_edge.attr,
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&format_attr_filter_brand0.attr,
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&format_attr_filter_brand1.attr,
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&format_attr_filter_brand2.attr,
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&format_attr_filter_brand3.attr,
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NULL,
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};
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@ -203,6 +304,11 @@ static struct attribute_group snbep_uncore_ubox_format_group = {
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.attrs = snbep_uncore_ubox_formats_attr,
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};
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static struct attribute_group snbep_uncore_cbox_format_group = {
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.name = "format",
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.attrs = snbep_uncore_cbox_formats_attr,
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};
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static struct attribute_group snbep_uncore_pcu_format_group = {
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.name = "format",
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.attrs = snbep_uncore_pcu_formats_attr,
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@ -215,6 +321,9 @@ static struct intel_uncore_ops snbep_uncore_msr_ops = {
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.disable_event = snbep_uncore_msr_disable_event,
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.enable_event = snbep_uncore_msr_enable_event,
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.read_counter = snbep_uncore_msr_read_counter,
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.get_constraint = snbep_uncore_get_constraint,
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.put_constraint = snbep_uncore_put_constraint,
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.hw_config = snbep_uncore_hw_config,
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};
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static struct intel_uncore_ops snbep_uncore_pci_ops = {
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@ -307,31 +416,33 @@ static struct intel_uncore_type snbep_uncore_ubox = {
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};
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static struct intel_uncore_type snbep_uncore_cbox = {
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.name = "cbox",
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.num_counters = 4,
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.num_boxes = 8,
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.perf_ctr_bits = 44,
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.event_ctl = SNBEP_C0_MSR_PMON_CTL0,
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.perf_ctr = SNBEP_C0_MSR_PMON_CTR0,
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.event_mask = SNBEP_PMON_RAW_EVENT_MASK,
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.box_ctl = SNBEP_C0_MSR_PMON_BOX_CTL,
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.msr_offset = SNBEP_CBO_MSR_OFFSET,
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.constraints = snbep_uncore_cbox_constraints,
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.ops = &snbep_uncore_msr_ops,
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.format_group = &snbep_uncore_format_group,
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.name = "cbox",
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.num_counters = 4,
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.num_boxes = 8,
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.perf_ctr_bits = 44,
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.event_ctl = SNBEP_C0_MSR_PMON_CTL0,
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.perf_ctr = SNBEP_C0_MSR_PMON_CTR0,
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.event_mask = SNBEP_CBO_MSR_PMON_RAW_EVENT_MASK,
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.box_ctl = SNBEP_C0_MSR_PMON_BOX_CTL,
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.msr_offset = SNBEP_CBO_MSR_OFFSET,
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.num_shared_regs = 1,
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.constraints = snbep_uncore_cbox_constraints,
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.ops = &snbep_uncore_msr_ops,
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.format_group = &snbep_uncore_cbox_format_group,
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};
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static struct intel_uncore_type snbep_uncore_pcu = {
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.name = "pcu",
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.num_counters = 4,
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.num_boxes = 1,
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.perf_ctr_bits = 48,
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.perf_ctr = SNBEP_PCU_MSR_PMON_CTR0,
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.event_ctl = SNBEP_PCU_MSR_PMON_CTL0,
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.event_mask = SNBEP_PCU_MSR_PMON_RAW_EVENT_MASK,
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.box_ctl = SNBEP_PCU_MSR_PMON_BOX_CTL,
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.ops = &snbep_uncore_msr_ops,
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.format_group = &snbep_uncore_pcu_format_group,
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.name = "pcu",
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.num_counters = 4,
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.num_boxes = 1,
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.perf_ctr_bits = 48,
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.perf_ctr = SNBEP_PCU_MSR_PMON_CTR0,
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.event_ctl = SNBEP_PCU_MSR_PMON_CTL0,
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.event_mask = SNBEP_PCU_MSR_PMON_RAW_EVENT_MASK,
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.box_ctl = SNBEP_PCU_MSR_PMON_BOX_CTL,
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.num_shared_regs = 1,
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.ops = &snbep_uncore_msr_ops,
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.format_group = &snbep_uncore_pcu_format_group,
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};
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static struct intel_uncore_type *snbep_msr_uncores[] = {
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@ -747,15 +858,22 @@ static void uncore_pmu_init_hrtimer(struct intel_uncore_box *box)
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box->hrtimer.function = uncore_pmu_hrtimer;
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}
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struct intel_uncore_box *uncore_alloc_box(int cpu)
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struct intel_uncore_box *uncore_alloc_box(struct intel_uncore_type *type,
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int cpu)
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{
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struct intel_uncore_box *box;
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int i, size;
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box = kmalloc_node(sizeof(*box), GFP_KERNEL | __GFP_ZERO,
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cpu_to_node(cpu));
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size = sizeof(*box) + type->num_shared_regs *
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sizeof(struct intel_uncore_extra_reg);
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box = kmalloc_node(size, GFP_KERNEL | __GFP_ZERO, cpu_to_node(cpu));
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if (!box)
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return NULL;
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for (i = 0; i < type->num_shared_regs; i++)
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raw_spin_lock_init(&box->shared_regs[i].lock);
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uncore_pmu_init_hrtimer(box);
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atomic_set(&box->refcnt, 1);
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box->cpu = -1;
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@ -834,11 +952,18 @@ static int uncore_collect_events(struct intel_uncore_box *box,
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}
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static struct event_constraint *
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uncore_event_constraint(struct intel_uncore_type *type,
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struct perf_event *event)
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uncore_get_event_constraint(struct intel_uncore_box *box,
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struct perf_event *event)
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{
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struct intel_uncore_type *type = box->pmu->type;
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struct event_constraint *c;
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if (type->ops->get_constraint) {
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c = type->ops->get_constraint(box, event);
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if (c)
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return c;
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}
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if (event->hw.config == ~0ULL)
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return &constraint_fixed;
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@ -852,19 +977,25 @@ uncore_event_constraint(struct intel_uncore_type *type,
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return &type->unconstrainted;
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}
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static void uncore_put_event_constraint(struct intel_uncore_box *box,
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struct perf_event *event)
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{
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if (box->pmu->type->ops->put_constraint)
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box->pmu->type->ops->put_constraint(box, event);
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}
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static int uncore_assign_events(struct intel_uncore_box *box,
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int assign[], int n)
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{
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unsigned long used_mask[BITS_TO_LONGS(UNCORE_PMC_IDX_MAX)];
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struct event_constraint *c, *constraints[UNCORE_PMC_IDX_MAX];
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int i, ret, wmin, wmax;
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int i, wmin, wmax, ret = 0;
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struct hw_perf_event *hwc;
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bitmap_zero(used_mask, UNCORE_PMC_IDX_MAX);
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for (i = 0, wmin = UNCORE_PMC_IDX_MAX, wmax = 0; i < n; i++) {
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c = uncore_event_constraint(box->pmu->type,
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box->event_list[i]);
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c = uncore_get_event_constraint(box, box->event_list[i]);
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constraints[i] = c;
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wmin = min(wmin, c->weight);
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wmax = max(wmax, c->weight);
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@ -888,13 +1019,17 @@ static int uncore_assign_events(struct intel_uncore_box *box,
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break;
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__set_bit(hwc->idx, used_mask);
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assign[i] = hwc->idx;
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if (assign)
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assign[i] = hwc->idx;
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}
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if (i == n)
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return 0;
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/* slow path */
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ret = perf_assign_events(constraints, n, wmin, wmax, assign);
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if (i != n)
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ret = perf_assign_events(constraints, n, wmin, wmax, assign);
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if (!assign || ret) {
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for (i = 0; i < n; i++)
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uncore_put_event_constraint(box, box->event_list[i]);
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}
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return ret ? -EINVAL : 0;
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}
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@ -1021,6 +1156,8 @@ static void uncore_pmu_event_del(struct perf_event *event, int flags)
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for (i = 0; i < box->n_events; i++) {
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if (event == box->event_list[i]) {
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uncore_put_event_constraint(box, event);
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while (++i < box->n_events)
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box->event_list[i - 1] = box->event_list[i];
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@ -1048,10 +1185,9 @@ static int uncore_validate_group(struct intel_uncore_pmu *pmu,
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{
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struct perf_event *leader = event->group_leader;
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struct intel_uncore_box *fake_box;
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int assign[UNCORE_PMC_IDX_MAX];
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int ret = -EINVAL, n;
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fake_box = uncore_alloc_box(smp_processor_id());
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fake_box = uncore_alloc_box(pmu->type, smp_processor_id());
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if (!fake_box)
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return -ENOMEM;
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@ -1073,7 +1209,7 @@ static int uncore_validate_group(struct intel_uncore_pmu *pmu,
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fake_box->n_events = n;
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ret = uncore_assign_events(fake_box, assign, n);
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ret = uncore_assign_events(fake_box, NULL, n);
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out:
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kfree(fake_box);
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return ret;
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@ -1117,6 +1253,10 @@ int uncore_pmu_event_init(struct perf_event *event)
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return -EINVAL;
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event->cpu = box->cpu;
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event->hw.idx = -1;
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event->hw.last_tag = ~0ULL;
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event->hw.extra_reg.idx = EXTRA_REG_NONE;
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if (event->attr.config == UNCORE_FIXED_EVENT) {
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/* no fixed counter */
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if (!pmu->type->fixed_ctl)
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@ -1130,11 +1270,13 @@ int uncore_pmu_event_init(struct perf_event *event)
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hwc->config = ~0ULL;
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} else {
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hwc->config = event->attr.config & pmu->type->event_mask;
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if (pmu->type->ops->hw_config) {
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ret = pmu->type->ops->hw_config(box, event);
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if (ret)
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return ret;
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}
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}
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event->hw.idx = -1;
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event->hw.last_tag = ~0ULL;
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if (event->group_leader != event)
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ret = uncore_validate_group(pmu, event);
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else
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@ -1276,7 +1418,7 @@ static int __devinit uncore_pci_add(struct intel_uncore_type *type,
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if (phys_id < 0)
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return -ENODEV;
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box = uncore_alloc_box(0);
|
||||
box = uncore_alloc_box(type, 0);
|
||||
if (!box)
|
||||
return -ENOMEM;
|
||||
|
||||
|
|
@ -1458,7 +1600,7 @@ static int __cpuinit uncore_cpu_prepare(int cpu, int phys_id)
|
|||
if (pmu->func_id < 0)
|
||||
pmu->func_id = j;
|
||||
|
||||
box = uncore_alloc_box(cpu);
|
||||
box = uncore_alloc_box(type, cpu);
|
||||
if (!box)
|
||||
return -ENOMEM;
|
||||
|
||||
|
|
|
|||
|
|
@ -97,6 +97,10 @@
|
|||
SNBEP_PMON_CTL_INVERT | \
|
||||
SNBEP_U_MSR_PMON_CTL_TRESH_MASK)
|
||||
|
||||
#define SNBEP_CBO_PMON_CTL_TID_EN (1 << 19)
|
||||
#define SNBEP_CBO_MSR_PMON_RAW_EVENT_MASK (SNBEP_PMON_RAW_EVENT_MASK | \
|
||||
SNBEP_CBO_PMON_CTL_TID_EN)
|
||||
|
||||
/* SNB-EP PCU event control */
|
||||
#define SNBEP_PCU_MSR_PMON_CTL_OCC_SEL_MASK 0x0000c000
|
||||
#define SNBEP_PCU_MSR_PMON_CTL_TRESH_MASK 0x1f000000
|
||||
|
|
@ -140,15 +144,17 @@
|
|||
/* SNB-EP Cbo register */
|
||||
#define SNBEP_C0_MSR_PMON_CTR0 0xd16
|
||||
#define SNBEP_C0_MSR_PMON_CTL0 0xd10
|
||||
#define SNBEP_C0_MSR_PMON_BOX_FILTER 0xd14
|
||||
#define SNBEP_C0_MSR_PMON_BOX_CTL 0xd04
|
||||
#define SNBEP_C0_MSR_PMON_BOX_FILTER 0xd14
|
||||
#define SNBEP_CB0_MSR_PMON_BOX_FILTER_MASK 0xfffffc1f
|
||||
#define SNBEP_CBO_MSR_OFFSET 0x20
|
||||
|
||||
/* SNB-EP PCU register */
|
||||
#define SNBEP_PCU_MSR_PMON_CTR0 0xc36
|
||||
#define SNBEP_PCU_MSR_PMON_CTL0 0xc30
|
||||
#define SNBEP_PCU_MSR_PMON_BOX_FILTER 0xc34
|
||||
#define SNBEP_PCU_MSR_PMON_BOX_CTL 0xc24
|
||||
#define SNBEP_PCU_MSR_PMON_BOX_FILTER 0xc34
|
||||
#define SNBEP_PCU_MSR_PMON_BOX_FILTER_MASK 0xffffffff
|
||||
#define SNBEP_PCU_MSR_CORE_C3_CTR 0x3fc
|
||||
#define SNBEP_PCU_MSR_CORE_C6_CTR 0x3fd
|
||||
|
||||
|
|
@ -163,7 +169,6 @@ struct intel_uncore_type {
|
|||
int num_boxes;
|
||||
int perf_ctr_bits;
|
||||
int fixed_ctr_bits;
|
||||
int single_fixed;
|
||||
unsigned perf_ctr;
|
||||
unsigned event_ctl;
|
||||
unsigned event_mask;
|
||||
|
|
@ -171,6 +176,8 @@ struct intel_uncore_type {
|
|||
unsigned fixed_ctl;
|
||||
unsigned box_ctl;
|
||||
unsigned msr_offset;
|
||||
unsigned num_shared_regs:8;
|
||||
unsigned single_fixed:1;
|
||||
struct event_constraint unconstrainted;
|
||||
struct event_constraint *constraints;
|
||||
struct intel_uncore_pmu *pmus;
|
||||
|
|
@ -188,6 +195,10 @@ struct intel_uncore_ops {
|
|||
void (*disable_event)(struct intel_uncore_box *, struct perf_event *);
|
||||
void (*enable_event)(struct intel_uncore_box *, struct perf_event *);
|
||||
u64 (*read_counter)(struct intel_uncore_box *, struct perf_event *);
|
||||
int (*hw_config)(struct intel_uncore_box *, struct perf_event *);
|
||||
struct event_constraint *(*get_constraint)(struct intel_uncore_box *,
|
||||
struct perf_event *);
|
||||
void (*put_constraint)(struct intel_uncore_box *, struct perf_event *);
|
||||
};
|
||||
|
||||
struct intel_uncore_pmu {
|
||||
|
|
@ -200,6 +211,12 @@ struct intel_uncore_pmu {
|
|||
struct list_head box_list;
|
||||
};
|
||||
|
||||
struct intel_uncore_extra_reg {
|
||||
raw_spinlock_t lock;
|
||||
u64 config1;
|
||||
atomic_t ref;
|
||||
};
|
||||
|
||||
struct intel_uncore_box {
|
||||
int phys_id;
|
||||
int n_active; /* number of active events */
|
||||
|
|
@ -215,6 +232,7 @@ struct intel_uncore_box {
|
|||
struct intel_uncore_pmu *pmu;
|
||||
struct hrtimer hrtimer;
|
||||
struct list_head list;
|
||||
struct intel_uncore_extra_reg shared_regs[0];
|
||||
};
|
||||
|
||||
#define UNCORE_BOX_FLAG_INITIATED 0
|
||||
|
|
|
|||
Loading…
Reference in New Issue