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drm: rcar-du: Support up to 4 CRTCs 

The Gen3 R8A7795 DU has 4 CRTCs, support them all.

Signed-off-by: Koji Matsuoka <koji.matsuoka.xm@renesas.com>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
hifive-unleashed-5.1
Koji Matsuoka 2015-09-04 19:49:05 +09:00 committed by Laurent Pinchart
parent dadab320e0
commit 6a8c49fc4a
3 changed files with 3 additions and 2 deletions
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2
drivers/gpu/drm/rcar-du/rcar_du_crtc.c
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@ -571,7 +571,7 @@ static irqreturn_t rcar_du_crtc_irq(int irq, void *arg)
int rcar_du_crtc_create(struct rcar_du_group *rgrp, unsigned int index)
{
static const unsigned int mmio_offsets[] = {
DU0_REG_OFFSET, DU1_REG_OFFSET, DU2_REG_OFFSET
DU0_REG_OFFSET, DU1_REG_OFFSET, DU2_REG_OFFSET, DU3_REG_OFFSET
};
struct rcar_du_device *rcdu = rgrp->dev;

2
drivers/gpu/drm/rcar-du/rcar_du_drv.h
View File

@ -67,7 +67,7 @@ struct rcar_du_device_info {
unsigned int num_lvds;
};
#define RCAR_DU_MAX_CRTCS 3
#define RCAR_DU_MAX_CRTCS 4
#define RCAR_DU_MAX_GROUPS DIV_ROUND_UP(RCAR_DU_MAX_CRTCS, 2)
#define RCAR_DU_MAX_LVDS 2
#define RCAR_DU_MAX_VSPS 4

1
drivers/gpu/drm/rcar-du/rcar_du_regs.h
View File

@ -16,6 +16,7 @@
#define DU0_REG_OFFSET 0x00000
#define DU1_REG_OFFSET 0x30000
#define DU2_REG_OFFSET 0x40000
#define DU3_REG_OFFSET 0x70000
/* -----------------------------------------------------------------------------
* Display Control Registers