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Merge branch 'mv88e6060-cleanups'

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Andrew Lunn says:

====================
mv88e6060 cleanups

This patchset performs some cleanups of the mv88e6060 DSA driver, as a
step towards making it an MDIO device, rather than use the old probing
method. The changes here are all pretty mechanical and only compile
tested.
====================

Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller 2019-04-27 20:23:05 -04:00
parent e56e251566 1ba22bf547
commit 6acda8fbbd
2 changed files with 67 additions and 66 deletions
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132
drivers/net/dsa/mv88e6060.c
View file

@ -1,11 +1,7 @@
// SPDX-License-Identifier: GPL-2.0+
/* /*
* net/dsa/mv88e6060.c - Driver for Marvell 88e6060 switch chips * net/dsa/mv88e6060.c - Driver for Marvell 88e6060 switch chips
* Copyright (c) 2008-2009 Marvell Semiconductor * Copyright (c) 2008-2009 Marvell Semiconductor
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*/ */
#include <linux/delay.h> #include <linux/delay.h>
@ -18,40 +14,16 @@
#include <net/dsa.h> #include <net/dsa.h>
#include "mv88e6060.h" #include "mv88e6060.h"
static int reg_read(struct dsa_switch *ds, int addr, int reg) static int reg_read(struct mv88e6060_priv *priv, int addr, int reg)
{ {
struct mv88e6060_priv *priv = ds->priv;
return mdiobus_read_nested(priv->bus, priv->sw_addr + addr, reg); return mdiobus_read_nested(priv->bus, priv->sw_addr + addr, reg);
} }
#define REG_READ(addr, reg) \ static int reg_write(struct mv88e6060_priv *priv, int addr, int reg, u16 val)
({ \
int __ret; \
\
__ret = reg_read(ds, addr, reg); \
if (__ret < 0) \
return __ret; \
__ret; \
})
static int reg_write(struct dsa_switch *ds, int addr, int reg, u16 val)
{ {
struct mv88e6060_priv *priv = ds->priv;
return mdiobus_write_nested(priv->bus, priv->sw_addr + addr, reg, val); return mdiobus_write_nested(priv->bus, priv->sw_addr + addr, reg, val);
} }
#define REG_WRITE(addr, reg, val) \
({ \
int __ret; \
\
__ret = reg_write(ds, addr, reg, val); \
if (__ret < 0) \
return __ret; \
})
static const char *mv88e6060_get_name(struct mii_bus *bus, int sw_addr) static const char *mv88e6060_get_name(struct mii_bus *bus, int sw_addr)
{ {
int ret; int ret;
@ -97,7 +69,7 @@ static const char *mv88e6060_drv_probe(struct device *dsa_dev,
return name; return name;
} }
static int mv88e6060_switch_reset(struct dsa_switch *ds) static int mv88e6060_switch_reset(struct mv88e6060_priv *priv)
{ {
int i; int i;
int ret; int ret;
@ -105,23 +77,32 @@ static int mv88e6060_switch_reset(struct dsa_switch *ds)
/* Set all ports to the disabled state. */ /* Set all ports to the disabled state. */
for (i = 0; i < MV88E6060_PORTS; i++) { for (i = 0; i < MV88E6060_PORTS; i++) {
ret = REG_READ(REG_PORT(i), PORT_CONTROL); ret = reg_read(priv, REG_PORT(i), PORT_CONTROL);
REG_WRITE(REG_PORT(i), PORT_CONTROL, if (ret < 0)
ret & ~PORT_CONTROL_STATE_MASK); return ret;
ret = reg_write(priv, REG_PORT(i), PORT_CONTROL,
ret & ~PORT_CONTROL_STATE_MASK);
if (ret)
return ret;
} }
/* Wait for transmit queues to drain. */ /* Wait for transmit queues to drain. */
usleep_range(2000, 4000); usleep_range(2000, 4000);
/* Reset the switch. */ /* Reset the switch. */
REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL, ret = reg_write(priv, REG_GLOBAL, GLOBAL_ATU_CONTROL,
GLOBAL_ATU_CONTROL_SWRESET | GLOBAL_ATU_CONTROL_SWRESET |
GLOBAL_ATU_CONTROL_LEARNDIS); GLOBAL_ATU_CONTROL_LEARNDIS);
if (ret)
return ret;
/* Wait up to one second for reset to complete. */ /* Wait up to one second for reset to complete. */
timeout = jiffies + 1 * HZ; timeout = jiffies + 1 * HZ;
while (time_before(jiffies, timeout)) { while (time_before(jiffies, timeout)) {
ret = REG_READ(REG_GLOBAL, GLOBAL_STATUS); ret = reg_read(priv, REG_GLOBAL, GLOBAL_STATUS);
if (ret < 0)
return ret;
if (ret & GLOBAL_STATUS_INIT_READY) if (ret & GLOBAL_STATUS_INIT_READY)
break; break;
@ -133,61 +114,69 @@ static int mv88e6060_switch_reset(struct dsa_switch *ds)
return 0; return 0;
} }
static int mv88e6060_setup_global(struct dsa_switch *ds) static int mv88e6060_setup_global(struct mv88e6060_priv *priv)
{ {
int ret;
/* Disable discarding of frames with excessive collisions, /* Disable discarding of frames with excessive collisions,
* set the maximum frame size to 1536 bytes, and mask all * set the maximum frame size to 1536 bytes, and mask all
* interrupt sources. * interrupt sources.
*/ */
REG_WRITE(REG_GLOBAL, GLOBAL_CONTROL, GLOBAL_CONTROL_MAX_FRAME_1536); ret = reg_write(priv, REG_GLOBAL, GLOBAL_CONTROL,
GLOBAL_CONTROL_MAX_FRAME_1536);
if (ret)
return ret;
/* Disable automatic address learning. /* Disable automatic address learning.
*/ */
REG_WRITE(REG_GLOBAL, GLOBAL_ATU_CONTROL, return reg_write(priv, REG_GLOBAL, GLOBAL_ATU_CONTROL,
GLOBAL_ATU_CONTROL_LEARNDIS); GLOBAL_ATU_CONTROL_LEARNDIS);
return 0;
} }
static int mv88e6060_setup_port(struct dsa_switch *ds, int p) static int mv88e6060_setup_port(struct mv88e6060_priv *priv, int p)
{ {
int addr = REG_PORT(p); int addr = REG_PORT(p);
int ret;
/* Do not force flow control, disable Ingress and Egress /* Do not force flow control, disable Ingress and Egress
* Header tagging, disable VLAN tunneling, and set the port * Header tagging, disable VLAN tunneling, and set the port
* state to Forwarding. Additionally, if this is the CPU * state to Forwarding. Additionally, if this is the CPU
* port, enable Ingress and Egress Trailer tagging mode. * port, enable Ingress and Egress Trailer tagging mode.
*/ */
REG_WRITE(addr, PORT_CONTROL, ret = reg_write(priv, addr, PORT_CONTROL,
dsa_is_cpu_port(ds, p) ? dsa_is_cpu_port(priv->ds, p) ?
PORT_CONTROL_TRAILER | PORT_CONTROL_TRAILER |
PORT_CONTROL_INGRESS_MODE | PORT_CONTROL_INGRESS_MODE |
PORT_CONTROL_STATE_FORWARDING : PORT_CONTROL_STATE_FORWARDING :
PORT_CONTROL_STATE_FORWARDING); PORT_CONTROL_STATE_FORWARDING);
if (ret)
return ret;
/* Port based VLAN map: give each port its own address /* Port based VLAN map: give each port its own address
* database, allow the CPU port to talk to each of the 'real' * database, allow the CPU port to talk to each of the 'real'
* ports, and allow each of the 'real' ports to only talk to * ports, and allow each of the 'real' ports to only talk to
* the CPU port. * the CPU port.
*/ */
REG_WRITE(addr, PORT_VLAN_MAP, ret = reg_write(priv, addr, PORT_VLAN_MAP,
((p & 0xf) << PORT_VLAN_MAP_DBNUM_SHIFT) | ((p & 0xf) << PORT_VLAN_MAP_DBNUM_SHIFT) |
(dsa_is_cpu_port(ds, p) ? dsa_user_ports(ds) : (dsa_is_cpu_port(priv->ds, p) ?
BIT(dsa_to_port(ds, p)->cpu_dp->index))); dsa_user_ports(priv->ds) :
BIT(dsa_to_port(priv->ds, p)->cpu_dp->index)));
if (ret)
return ret;
/* Port Association Vector: when learning source addresses /* Port Association Vector: when learning source addresses
* of packets, add the address to the address database using * of packets, add the address to the address database using
* a port bitmap that has only the bit for this port set and * a port bitmap that has only the bit for this port set and
* the other bits clear. * the other bits clear.
*/ */
REG_WRITE(addr, PORT_ASSOC_VECTOR, BIT(p)); return reg_write(priv, addr, PORT_ASSOC_VECTOR, BIT(p));
return 0;
} }
static int mv88e6060_setup_addr(struct dsa_switch *ds) static int mv88e6060_setup_addr(struct mv88e6060_priv *priv)
{ {
u8 addr[ETH_ALEN]; u8 addr[ETH_ALEN];
int ret;
u16 val; u16 val;
eth_random_addr(addr); eth_random_addr(addr);
@ -199,34 +188,43 @@ static int mv88e6060_setup_addr(struct dsa_switch *ds)
*/ */
val &= 0xfeff; val &= 0xfeff;
REG_WRITE(REG_GLOBAL, GLOBAL_MAC_01, val); ret = reg_write(priv, REG_GLOBAL, GLOBAL_MAC_01, val);
REG_WRITE(REG_GLOBAL, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]); if (ret)
REG_WRITE(REG_GLOBAL, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]); return ret;
return 0; ret = reg_write(priv, REG_GLOBAL, GLOBAL_MAC_23,
(addr[2] << 8) | addr[3]);
if (ret)
return ret;
return reg_write(priv, REG_GLOBAL, GLOBAL_MAC_45,
(addr[4] << 8) | addr[5]);
} }
static int mv88e6060_setup(struct dsa_switch *ds) static int mv88e6060_setup(struct dsa_switch *ds)
{ {
struct mv88e6060_priv *priv = ds->priv;
int ret; int ret;
int i; int i;
ret = mv88e6060_switch_reset(ds); priv->ds = ds;
ret = mv88e6060_switch_reset(priv);
if (ret < 0) if (ret < 0)
return ret; return ret;
/* @@@ initialise atu */ /* @@@ initialise atu */
ret = mv88e6060_setup_global(ds); ret = mv88e6060_setup_global(priv);
if (ret < 0) if (ret < 0)
return ret; return ret;
ret = mv88e6060_setup_addr(ds); ret = mv88e6060_setup_addr(priv);
if (ret < 0) if (ret < 0)
return ret; return ret;
for (i = 0; i < MV88E6060_PORTS; i++) { for (i = 0; i < MV88E6060_PORTS; i++) {
ret = mv88e6060_setup_port(ds, i); ret = mv88e6060_setup_port(priv, i);
if (ret < 0) if (ret < 0)
return ret; return ret;
} }
@ -243,25 +241,27 @@ static int mv88e6060_port_to_phy_addr(int port)
static int mv88e6060_phy_read(struct dsa_switch *ds, int port, int regnum) static int mv88e6060_phy_read(struct dsa_switch *ds, int port, int regnum)
{ {
struct mv88e6060_priv *priv = ds->priv;
int addr; int addr;
addr = mv88e6060_port_to_phy_addr(port); addr = mv88e6060_port_to_phy_addr(port);
if (addr == -1) if (addr == -1)
return 0xffff; return 0xffff;
return reg_read(ds, addr, regnum); return reg_read(priv, addr, regnum);
} }
static int static int
mv88e6060_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val) mv88e6060_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
{ {
struct mv88e6060_priv *priv = ds->priv;
int addr; int addr;
addr = mv88e6060_port_to_phy_addr(port); addr = mv88e6060_port_to_phy_addr(port);
if (addr == -1) if (addr == -1)
return 0xffff; return 0xffff;
return reg_write(ds, addr, regnum, val); return reg_write(priv, addr, regnum, val);
} }
static const struct dsa_switch_ops mv88e6060_switch_ops = { static const struct dsa_switch_ops mv88e6060_switch_ops = {

1
drivers/net/dsa/mv88e6060.h
View file

@ -117,6 +117,7 @@ struct mv88e6060_priv {
*/ */
struct mii_bus *bus; struct mii_bus *bus;
int sw_addr; int sw_addr;
struct dsa_switch *ds;
}; };
#endif #endif