watchdog: bcm281xx: Watchdog Driver
This commit adds support for the watchdog timer used on the BCM281xx family of SoCs. Signed-off-by: Markus Mayer <markus.mayer@linaro.org> Reviewed-by: Matt Porter <matt.porter@linaro.org> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@iguana.be>hifive-unleashed-5.1
Markus Mayer
Wim Van Sebroeck
parent
2c34d59916
commit
6adb730dc2
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@ -126,3 +126,5 @@ CONFIG_CRC7=y
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CONFIG_XZ_DEC=y
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CONFIG_AVERAGE=y
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CONFIG_PINCTRL_CAPRI=y
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CONFIG_WATCHDOG=y
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CONFIG_BCM_KONA_WDT=y
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@ -1139,6 +1139,18 @@ config BCM2835_WDT
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To compile this driver as a loadable module, choose M here.
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The module will be called bcm2835_wdt.
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config BCM_KONA_WDT
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tristate "BCM Kona Watchdog"
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depends on ARCH_BCM
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select WATCHDOG_CORE
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help
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Support for the watchdog timer on the following Broadcom BCM281xx
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family, which includes BCM11130, BCM11140, BCM11351, BCM28145 and
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BCM28155 variants.
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Say 'Y' or 'M' here to enable the driver. The module will be called
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bcm_kona_wdt.
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config LANTIQ_WDT
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tristate "Lantiq SoC watchdog"
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depends on LANTIQ
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@ -57,6 +57,7 @@ obj-$(CONFIG_RETU_WATCHDOG) += retu_wdt.o
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obj-$(CONFIG_BCM2835_WDT) += bcm2835_wdt.o
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obj-$(CONFIG_MOXART_WDT) += moxart_wdt.o
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obj-$(CONFIG_SIRFSOC_WATCHDOG) += sirfsoc_wdt.o
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obj-$(CONFIG_BCM_KONA_WDT) += bcm_kona_wdt.o
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# AVR32 Architecture
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obj-$(CONFIG_AT32AP700X_WDT) += at32ap700x_wdt.o
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@ -0,0 +1,268 @@
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/*
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* Copyright (C) 2013 Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include <linux/watchdog.h>
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#define SECWDOG_CTRL_REG 0x00000000
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#define SECWDOG_COUNT_REG 0x00000004
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#define SECWDOG_RESERVED_MASK 0x1dffffff
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#define SECWDOG_WD_LOAD_FLAG 0x10000000
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#define SECWDOG_EN_MASK 0x08000000
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#define SECWDOG_SRSTEN_MASK 0x04000000
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#define SECWDOG_RES_MASK 0x00f00000
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#define SECWDOG_COUNT_MASK 0x000fffff
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#define SECWDOG_MAX_COUNT SECWDOG_COUNT_MASK
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#define SECWDOG_CLKS_SHIFT 20
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#define SECWDOG_MAX_RES 15
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#define SECWDOG_DEFAULT_RESOLUTION 4
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#define SECWDOG_MAX_TRY 1000
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#define SECS_TO_TICKS(x, w) ((x) << (w)->resolution)
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#define TICKS_TO_SECS(x, w) ((x) >> (w)->resolution)
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#define BCM_KONA_WDT_NAME "bcm_kona_wdt"
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struct bcm_kona_wdt {
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void __iomem *base;
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/*
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* One watchdog tick is 1/(2^resolution) seconds. Resolution can take
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* the values 0-15, meaning one tick can be 1s to 30.52us. Our default
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* resolution of 4 means one tick is 62.5ms.
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*
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* The watchdog counter is 20 bits. Depending on resolution, the maximum
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* counter value of 0xfffff expires after about 12 days (resolution 0)
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* down to only 32s (resolution 15). The default resolution of 4 gives
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* us a maximum of about 18 hours and 12 minutes before the watchdog
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* times out.
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*/
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int resolution;
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spinlock_t lock;
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};
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static int secure_register_read(void __iomem *addr)
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{
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uint32_t val;
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unsigned count = 0;
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/*
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* If the WD_LOAD_FLAG is set, the watchdog counter field is being
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* updated in hardware. Once the WD timer is updated in hardware, it
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* gets cleared.
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*/
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do {
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if (unlikely(count > 1))
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udelay(5);
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val = readl_relaxed(addr);
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count++;
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} while ((val & SECWDOG_WD_LOAD_FLAG) && count < SECWDOG_MAX_TRY);
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/* This is the only place we return a negative value. */
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if (val & SECWDOG_WD_LOAD_FLAG)
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return -ETIMEDOUT;
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/* We always mask out reserved bits. */
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val &= SECWDOG_RESERVED_MASK;
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return val;
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}
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static int bcm_kona_wdt_ctrl_reg_modify(struct bcm_kona_wdt *wdt,
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unsigned mask, unsigned newval)
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{
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int val;
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unsigned long flags;
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int ret = 0;
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spin_lock_irqsave(&wdt->lock, flags);
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val = secure_register_read(wdt->base + SECWDOG_CTRL_REG);
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if (val < 0) {
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ret = val;
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} else {
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val &= ~mask;
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val |= newval;
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writel_relaxed(val, wdt->base + SECWDOG_CTRL_REG);
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}
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spin_unlock_irqrestore(&wdt->lock, flags);
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return ret;
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}
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static int bcm_kona_wdt_set_resolution_reg(struct bcm_kona_wdt *wdt)
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{
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if (wdt->resolution > SECWDOG_MAX_RES)
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return -EINVAL;
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return bcm_kona_wdt_ctrl_reg_modify(wdt, SECWDOG_RES_MASK,
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wdt->resolution << SECWDOG_CLKS_SHIFT);
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}
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static int bcm_kona_wdt_set_timeout_reg(struct watchdog_device *wdog,
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unsigned watchdog_flags)
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{
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struct bcm_kona_wdt *wdt = watchdog_get_drvdata(wdog);
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return bcm_kona_wdt_ctrl_reg_modify(wdt, SECWDOG_COUNT_MASK,
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SECS_TO_TICKS(wdog->timeout, wdt) |
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watchdog_flags);
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}
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static int bcm_kona_wdt_set_timeout(struct watchdog_device *wdog,
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unsigned int t)
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{
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wdog->timeout = t;
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return 0;
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}
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static unsigned int bcm_kona_wdt_get_timeleft(struct watchdog_device *wdog)
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{
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struct bcm_kona_wdt *wdt = watchdog_get_drvdata(wdog);
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int val;
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unsigned long flags;
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spin_lock_irqsave(&wdt->lock, flags);
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val = secure_register_read(wdt->base + SECWDOG_COUNT_REG);
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spin_unlock_irqrestore(&wdt->lock, flags);
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if (val < 0)
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return val;
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return TICKS_TO_SECS(val & SECWDOG_COUNT_MASK, wdt);
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}
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static int bcm_kona_wdt_start(struct watchdog_device *wdog)
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{
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return bcm_kona_wdt_set_timeout_reg(wdog,
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SECWDOG_EN_MASK | SECWDOG_SRSTEN_MASK);
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}
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static int bcm_kona_wdt_stop(struct watchdog_device *wdog)
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{
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struct bcm_kona_wdt *wdt = watchdog_get_drvdata(wdog);
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return bcm_kona_wdt_ctrl_reg_modify(wdt, SECWDOG_EN_MASK |
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SECWDOG_SRSTEN_MASK, 0);
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}
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static struct watchdog_ops bcm_kona_wdt_ops = {
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.owner = THIS_MODULE,
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.start = bcm_kona_wdt_start,
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.stop = bcm_kona_wdt_stop,
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.set_timeout = bcm_kona_wdt_set_timeout,
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.get_timeleft = bcm_kona_wdt_get_timeleft,
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};
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static struct watchdog_info bcm_kona_wdt_info = {
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.options = WDIOF_SETTIMEOUT | WDIOF_MAGICCLOSE |
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WDIOF_KEEPALIVEPING,
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.identity = "Broadcom Kona Watchdog Timer",
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};
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static struct watchdog_device bcm_kona_wdt_wdd = {
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.info = &bcm_kona_wdt_info,
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.ops = &bcm_kona_wdt_ops,
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.min_timeout = 1,
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.max_timeout = SECWDOG_MAX_COUNT >> SECWDOG_DEFAULT_RESOLUTION,
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.timeout = SECWDOG_MAX_COUNT >> SECWDOG_DEFAULT_RESOLUTION,
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};
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static void bcm_kona_wdt_shutdown(struct platform_device *pdev)
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{
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bcm_kona_wdt_stop(&bcm_kona_wdt_wdd);
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}
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static int bcm_kona_wdt_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct bcm_kona_wdt *wdt;
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struct resource *res;
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int ret;
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wdt = devm_kzalloc(dev, sizeof(*wdt), GFP_KERNEL);
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if (!wdt)
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return -ENOMEM;
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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wdt->base = devm_ioremap_resource(dev, res);
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if (IS_ERR(wdt->base))
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return -ENODEV;
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wdt->resolution = SECWDOG_DEFAULT_RESOLUTION;
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ret = bcm_kona_wdt_set_resolution_reg(wdt);
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if (ret) {
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dev_err(dev, "Failed to set resolution (error: %d)", ret);
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return ret;
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}
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spin_lock_init(&wdt->lock);
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platform_set_drvdata(pdev, wdt);
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watchdog_set_drvdata(&bcm_kona_wdt_wdd, wdt);
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ret = bcm_kona_wdt_set_timeout_reg(&bcm_kona_wdt_wdd, 0);
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if (ret) {
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dev_err(dev, "Failed set watchdog timeout");
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return ret;
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}
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ret = watchdog_register_device(&bcm_kona_wdt_wdd);
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if (ret) {
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dev_err(dev, "Failed to register watchdog device");
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return ret;
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}
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dev_dbg(dev, "Broadcom Kona Watchdog Timer");
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return 0;
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}
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static int bcm_kona_wdt_remove(struct platform_device *pdev)
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{
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bcm_kona_wdt_shutdown(pdev);
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watchdog_unregister_device(&bcm_kona_wdt_wdd);
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dev_dbg(&pdev->dev, "Watchdog driver disabled");
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return 0;
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}
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static const struct of_device_id bcm_kona_wdt_of_match[] = {
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{ .compatible = "brcm,kona-wdt", },
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{},
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};
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MODULE_DEVICE_TABLE(of, bcm_kona_wdt_of_match);
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static struct platform_driver bcm_kona_wdt_driver = {
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.driver = {
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.name = BCM_KONA_WDT_NAME,
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.owner = THIS_MODULE,
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.of_match_table = bcm_kona_wdt_of_match,
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},
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.probe = bcm_kona_wdt_probe,
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.remove = bcm_kona_wdt_remove,
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.shutdown = bcm_kona_wdt_shutdown,
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};
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module_platform_driver(bcm_kona_wdt_driver);
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MODULE_ALIAS("platform:" BCM_KONA_WDT_NAME);
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MODULE_AUTHOR("Markus Mayer <mmayer@broadcom.com>");
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MODULE_DESCRIPTION("Broadcom Kona Watchdog Driver");
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MODULE_LICENSE("GPL v2");
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