OMAP3 clock: remove wait for DPLL3 M2 clock to stabilize
The original CDP kernel that this code comes from waited for 0x800 loops after switching the CORE DPLL M2 divider. This does not appear to be necessary. Signed-off-by: Paul Walmsley <paul@pwsan.com>
This commit is contained in:
parent
cd07ecc828
commit
6adb8f388e
|
@ -102,9 +102,6 @@ configure_core_dpll:
|
|||
orr r12, r12, r3, lsl #0x1B @ r3 contains the M2 val
|
||||
str r12, [r11]
|
||||
ldr r12, [r11] @ posted-write barrier for CM
|
||||
mov r12, #0x800 @ wait for the clock to stabilise
|
||||
cmp r3, #2
|
||||
bne wait_clk_stable
|
||||
bx lr
|
||||
wait_clk_stable:
|
||||
subs r12, r12, #1
|
||||
|
|
Loading…
Reference in a new issue