Merge branch 'imx/pinctrl' into imx/dt
Conflicts: drivers/mmc/host/sdhci-esdhc-imx.c drivers/net/ethernet/freescale/fec.c drivers/spi/spi-imx.c drivers/tty/serial/imx.c This resolves some simply but annoying conflicts. Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
commit
6b204283f2
19
Documentation/ABI/testing/sysfs-bus-hsi
Normal file
19
Documentation/ABI/testing/sysfs-bus-hsi
Normal file
|
@ -0,0 +1,19 @@
|
|||
What: /sys/bus/hsi
|
||||
Date: April 2012
|
||||
KernelVersion: 3.4
|
||||
Contact: Carlos Chinea <carlos.chinea@nokia.com>
|
||||
Description:
|
||||
High Speed Synchronous Serial Interface (HSI) is a
|
||||
serial interface mainly used for connecting application
|
||||
engines (APE) with cellular modem engines (CMT) in cellular
|
||||
handsets.
|
||||
The bus will be populated with devices (hsi_clients) representing
|
||||
the protocols available in the system. Bus drivers implement
|
||||
those protocols.
|
||||
|
||||
What: /sys/bus/hsi/devices/.../modalias
|
||||
Date: April 2012
|
||||
KernelVersion: 3.4
|
||||
Contact: Carlos Chinea <carlos.chinea@nokia.com>
|
||||
Description: Stores the same MODALIAS value emitted by uevent
|
||||
Format: hsi:<hsi_client device name>
|
|
@ -9,7 +9,7 @@ architectures).
|
|||
|
||||
II. How does it work?
|
||||
|
||||
There are four per-task flags used for that, PF_NOFREEZE, PF_FROZEN, TIF_FREEZE
|
||||
There are three per-task flags used for that, PF_NOFREEZE, PF_FROZEN
|
||||
and PF_FREEZER_SKIP (the last one is auxiliary). The tasks that have
|
||||
PF_NOFREEZE unset (all user space processes and some kernel threads) are
|
||||
regarded as 'freezable' and treated in a special way before the system enters a
|
||||
|
@ -17,30 +17,31 @@ suspend state as well as before a hibernation image is created (in what follows
|
|||
we only consider hibernation, but the description also applies to suspend).
|
||||
|
||||
Namely, as the first step of the hibernation procedure the function
|
||||
freeze_processes() (defined in kernel/power/process.c) is called. It executes
|
||||
try_to_freeze_tasks() that sets TIF_FREEZE for all of the freezable tasks and
|
||||
either wakes them up, if they are kernel threads, or sends fake signals to them,
|
||||
if they are user space processes. A task that has TIF_FREEZE set, should react
|
||||
to it by calling the function called __refrigerator() (defined in
|
||||
kernel/freezer.c), which sets the task's PF_FROZEN flag, changes its state
|
||||
to TASK_UNINTERRUPTIBLE and makes it loop until PF_FROZEN is cleared for it.
|
||||
Then, we say that the task is 'frozen' and therefore the set of functions
|
||||
handling this mechanism is referred to as 'the freezer' (these functions are
|
||||
defined in kernel/power/process.c, kernel/freezer.c & include/linux/freezer.h).
|
||||
User space processes are generally frozen before kernel threads.
|
||||
freeze_processes() (defined in kernel/power/process.c) is called. A system-wide
|
||||
variable system_freezing_cnt (as opposed to a per-task flag) is used to indicate
|
||||
whether the system is to undergo a freezing operation. And freeze_processes()
|
||||
sets this variable. After this, it executes try_to_freeze_tasks() that sends a
|
||||
fake signal to all user space processes, and wakes up all the kernel threads.
|
||||
All freezable tasks must react to that by calling try_to_freeze(), which
|
||||
results in a call to __refrigerator() (defined in kernel/freezer.c), which sets
|
||||
the task's PF_FROZEN flag, changes its state to TASK_UNINTERRUPTIBLE and makes
|
||||
it loop until PF_FROZEN is cleared for it. Then, we say that the task is
|
||||
'frozen' and therefore the set of functions handling this mechanism is referred
|
||||
to as 'the freezer' (these functions are defined in kernel/power/process.c,
|
||||
kernel/freezer.c & include/linux/freezer.h). User space processes are generally
|
||||
frozen before kernel threads.
|
||||
|
||||
__refrigerator() must not be called directly. Instead, use the
|
||||
try_to_freeze() function (defined in include/linux/freezer.h), that checks
|
||||
the task's TIF_FREEZE flag and makes the task enter __refrigerator() if the
|
||||
flag is set.
|
||||
if the task is to be frozen and makes the task enter __refrigerator().
|
||||
|
||||
For user space processes try_to_freeze() is called automatically from the
|
||||
signal-handling code, but the freezable kernel threads need to call it
|
||||
explicitly in suitable places or use the wait_event_freezable() or
|
||||
wait_event_freezable_timeout() macros (defined in include/linux/freezer.h)
|
||||
that combine interruptible sleep with checking if TIF_FREEZE is set and calling
|
||||
try_to_freeze(). The main loop of a freezable kernel thread may look like the
|
||||
following one:
|
||||
that combine interruptible sleep with checking if the task is to be frozen and
|
||||
calling try_to_freeze(). The main loop of a freezable kernel thread may look
|
||||
like the following one:
|
||||
|
||||
set_freezable();
|
||||
do {
|
||||
|
@ -53,7 +54,7 @@ following one:
|
|||
(from drivers/usb/core/hub.c::hub_thread()).
|
||||
|
||||
If a freezable kernel thread fails to call try_to_freeze() after the freezer has
|
||||
set TIF_FREEZE for it, the freezing of tasks will fail and the entire
|
||||
initiated a freezing operation, the freezing of tasks will fail and the entire
|
||||
hibernation operation will be cancelled. For this reason, freezable kernel
|
||||
threads must call try_to_freeze() somewhere or use one of the
|
||||
wait_event_freezable() and wait_event_freezable_timeout() macros.
|
||||
|
|
|
@ -123,7 +123,7 @@ KEY SERVICE OVERVIEW
|
|||
|
||||
The key service provides a number of features besides keys:
|
||||
|
||||
(*) The key service defines two special key types:
|
||||
(*) The key service defines three special key types:
|
||||
|
||||
(+) "keyring"
|
||||
|
||||
|
@ -137,6 +137,18 @@ The key service provides a number of features besides keys:
|
|||
blobs of data. These can be created, updated and read by userspace,
|
||||
and aren't intended for use by kernel services.
|
||||
|
||||
(+) "logon"
|
||||
|
||||
Like a "user" key, a "logon" key has a payload that is an arbitrary
|
||||
blob of data. It is intended as a place to store secrets which are
|
||||
accessible to the kernel but not to userspace programs.
|
||||
|
||||
The description can be arbitrary, but must be prefixed with a non-zero
|
||||
length string that describes the key "subclass". The subclass is
|
||||
separated from the rest of the description by a ':'. "logon" keys can
|
||||
be created and updated from userspace, but the payload is only
|
||||
readable from kernel space.
|
||||
|
||||
(*) Each process subscribes to three keyrings: a thread-specific keyring, a
|
||||
process-specific keyring, and a session-specific keyring.
|
||||
|
||||
|
|
|
@ -3592,6 +3592,7 @@ S: Supported
|
|||
F: drivers/net/wireless/iwlegacy/
|
||||
|
||||
INTEL WIRELESS WIFI LINK (iwlwifi)
|
||||
M: Johannes Berg <johannes.berg@intel.com>
|
||||
M: Wey-Yi Guy <wey-yi.w.guy@intel.com>
|
||||
M: Intel Linux Wireless <ilw@linux.intel.com>
|
||||
L: linux-wireless@vger.kernel.org
|
||||
|
@ -7578,8 +7579,8 @@ F: Documentation/filesystems/xfs.txt
|
|||
F: fs/xfs/
|
||||
|
||||
XILINX AXI ETHERNET DRIVER
|
||||
M: Ariane Keller <ariane.keller@tik.ee.ethz.ch>
|
||||
M: Daniel Borkmann <daniel.borkmann@tik.ee.ethz.ch>
|
||||
M: Anirudha Sarangi <anirudh@xilinx.com>
|
||||
M: John Linn <John.Linn@xilinx.com>
|
||||
S: Maintained
|
||||
F: drivers/net/ethernet/xilinx/xilinx_axienet*
|
||||
|
||||
|
|
2
Makefile
2
Makefile
|
@ -1,7 +1,7 @@
|
|||
VERSION = 3
|
||||
PATCHLEVEL = 4
|
||||
SUBLEVEL = 0
|
||||
EXTRAVERSION = -rc4
|
||||
EXTRAVERSION = -rc5
|
||||
NAME = Saber-toothed Squirrel
|
||||
|
||||
# *DOCUMENTATION*
|
||||
|
|
|
@ -469,6 +469,7 @@ config ARCH_MXS
|
|||
select CLKDEV_LOOKUP
|
||||
select CLKSRC_MMIO
|
||||
select HAVE_CLK_PREPARE
|
||||
select PINCTRL
|
||||
help
|
||||
Support for Freescale MXS-based family of processors
|
||||
|
||||
|
|
|
@ -10,7 +10,7 @@
|
|||
intc: interrupt-controller@02080000 {
|
||||
compatible = "qcom,msm-8660-qgic";
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
#interrupt-cells = <3>;
|
||||
reg = < 0x02080000 0x1000 >,
|
||||
< 0x02081000 0x1000 >;
|
||||
};
|
||||
|
@ -19,6 +19,6 @@
|
|||
compatible = "qcom,msm-hsuart", "qcom,msm-uart";
|
||||
reg = <0x19c40000 0x1000>,
|
||||
<0x19c00000 0x1000>;
|
||||
interrupts = <195>;
|
||||
interrupts = <0 195 0x0>;
|
||||
};
|
||||
};
|
||||
|
|
|
@ -14,6 +14,8 @@ CONFIG_MODULE_FORCE_UNLOAD=y
|
|||
# CONFIG_BLK_DEV_BSG is not set
|
||||
CONFIG_BLK_DEV_INTEGRITY=y
|
||||
CONFIG_ARCH_S3C24XX=y
|
||||
# CONFIG_CPU_S3C2410 is not set
|
||||
CONFIG_CPU_S3C2440=y
|
||||
CONFIG_S3C_ADC=y
|
||||
CONFIG_S3C24XX_PWM=y
|
||||
CONFIG_MACH_MINI2440=y
|
||||
|
|
|
@ -118,14 +118,10 @@ static int twd_cpufreq_transition(struct notifier_block *nb,
|
|||
* The twd clock events must be reprogrammed to account for the new
|
||||
* frequency. The timer is local to a cpu, so cross-call to the
|
||||
* changing cpu.
|
||||
*
|
||||
* Only wait for it to finish, if the cpu is active to avoid
|
||||
* deadlock when cpu1 is spinning on while(!cpu_active(cpu1)) during
|
||||
* booting of that cpu.
|
||||
*/
|
||||
if (state == CPUFREQ_POSTCHANGE || state == CPUFREQ_RESUMECHANGE)
|
||||
smp_call_function_single(freqs->cpu, twd_update_frequency,
|
||||
NULL, cpu_active(freqs->cpu));
|
||||
NULL, 1);
|
||||
|
||||
return NOTIFY_OK;
|
||||
}
|
||||
|
|
|
@ -497,25 +497,25 @@ static struct clk exynos4_init_clocks_off[] = {
|
|||
.ctrlbit = (1 << 3),
|
||||
}, {
|
||||
.name = "hsmmc",
|
||||
.devname = "s3c-sdhci.0",
|
||||
.devname = "exynos4-sdhci.0",
|
||||
.parent = &exynos4_clk_aclk_133.clk,
|
||||
.enable = exynos4_clk_ip_fsys_ctrl,
|
||||
.ctrlbit = (1 << 5),
|
||||
}, {
|
||||
.name = "hsmmc",
|
||||
.devname = "s3c-sdhci.1",
|
||||
.devname = "exynos4-sdhci.1",
|
||||
.parent = &exynos4_clk_aclk_133.clk,
|
||||
.enable = exynos4_clk_ip_fsys_ctrl,
|
||||
.ctrlbit = (1 << 6),
|
||||
}, {
|
||||
.name = "hsmmc",
|
||||
.devname = "s3c-sdhci.2",
|
||||
.devname = "exynos4-sdhci.2",
|
||||
.parent = &exynos4_clk_aclk_133.clk,
|
||||
.enable = exynos4_clk_ip_fsys_ctrl,
|
||||
.ctrlbit = (1 << 7),
|
||||
}, {
|
||||
.name = "hsmmc",
|
||||
.devname = "s3c-sdhci.3",
|
||||
.devname = "exynos4-sdhci.3",
|
||||
.parent = &exynos4_clk_aclk_133.clk,
|
||||
.enable = exynos4_clk_ip_fsys_ctrl,
|
||||
.ctrlbit = (1 << 8),
|
||||
|
@ -1202,7 +1202,7 @@ static struct clksrc_clk exynos4_clk_sclk_uart3 = {
|
|||
static struct clksrc_clk exynos4_clk_sclk_mmc0 = {
|
||||
.clk = {
|
||||
.name = "sclk_mmc",
|
||||
.devname = "s3c-sdhci.0",
|
||||
.devname = "exynos4-sdhci.0",
|
||||
.parent = &exynos4_clk_dout_mmc0.clk,
|
||||
.enable = exynos4_clksrc_mask_fsys_ctrl,
|
||||
.ctrlbit = (1 << 0),
|
||||
|
@ -1213,7 +1213,7 @@ static struct clksrc_clk exynos4_clk_sclk_mmc0 = {
|
|||
static struct clksrc_clk exynos4_clk_sclk_mmc1 = {
|
||||
.clk = {
|
||||
.name = "sclk_mmc",
|
||||
.devname = "s3c-sdhci.1",
|
||||
.devname = "exynos4-sdhci.1",
|
||||
.parent = &exynos4_clk_dout_mmc1.clk,
|
||||
.enable = exynos4_clksrc_mask_fsys_ctrl,
|
||||
.ctrlbit = (1 << 4),
|
||||
|
@ -1224,7 +1224,7 @@ static struct clksrc_clk exynos4_clk_sclk_mmc1 = {
|
|||
static struct clksrc_clk exynos4_clk_sclk_mmc2 = {
|
||||
.clk = {
|
||||
.name = "sclk_mmc",
|
||||
.devname = "s3c-sdhci.2",
|
||||
.devname = "exynos4-sdhci.2",
|
||||
.parent = &exynos4_clk_dout_mmc2.clk,
|
||||
.enable = exynos4_clksrc_mask_fsys_ctrl,
|
||||
.ctrlbit = (1 << 8),
|
||||
|
@ -1235,7 +1235,7 @@ static struct clksrc_clk exynos4_clk_sclk_mmc2 = {
|
|||
static struct clksrc_clk exynos4_clk_sclk_mmc3 = {
|
||||
.clk = {
|
||||
.name = "sclk_mmc",
|
||||
.devname = "s3c-sdhci.3",
|
||||
.devname = "exynos4-sdhci.3",
|
||||
.parent = &exynos4_clk_dout_mmc3.clk,
|
||||
.enable = exynos4_clksrc_mask_fsys_ctrl,
|
||||
.ctrlbit = (1 << 12),
|
||||
|
@ -1340,10 +1340,10 @@ static struct clk_lookup exynos4_clk_lookup[] = {
|
|||
CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos4_clk_sclk_uart1.clk),
|
||||
CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos4_clk_sclk_uart2.clk),
|
||||
CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos4_clk_sclk_uart3.clk),
|
||||
CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk),
|
||||
CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk),
|
||||
CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk),
|
||||
CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk),
|
||||
CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos4_clk_sclk_mmc0.clk),
|
||||
CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos4_clk_sclk_mmc1.clk),
|
||||
CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos4_clk_sclk_mmc2.clk),
|
||||
CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos4_clk_sclk_mmc3.clk),
|
||||
CLKDEV_INIT("exynos4-fb.0", "lcd", &exynos4_clk_fimd0),
|
||||
CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos4_clk_pdma0),
|
||||
CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos4_clk_pdma1),
|
||||
|
|
|
@ -455,25 +455,25 @@ static struct clk exynos5_init_clocks_off[] = {
|
|||
.ctrlbit = (1 << 20),
|
||||
}, {
|
||||
.name = "hsmmc",
|
||||
.devname = "s3c-sdhci.0",
|
||||
.devname = "exynos4-sdhci.0",
|
||||
.parent = &exynos5_clk_aclk_200.clk,
|
||||
.enable = exynos5_clk_ip_fsys_ctrl,
|
||||
.ctrlbit = (1 << 12),
|
||||
}, {
|
||||
.name = "hsmmc",
|
||||
.devname = "s3c-sdhci.1",
|
||||
.devname = "exynos4-sdhci.1",
|
||||
.parent = &exynos5_clk_aclk_200.clk,
|
||||
.enable = exynos5_clk_ip_fsys_ctrl,
|
||||
.ctrlbit = (1 << 13),
|
||||
}, {
|
||||
.name = "hsmmc",
|
||||
.devname = "s3c-sdhci.2",
|
||||
.devname = "exynos4-sdhci.2",
|
||||
.parent = &exynos5_clk_aclk_200.clk,
|
||||
.enable = exynos5_clk_ip_fsys_ctrl,
|
||||
.ctrlbit = (1 << 14),
|
||||
}, {
|
||||
.name = "hsmmc",
|
||||
.devname = "s3c-sdhci.3",
|
||||
.devname = "exynos4-sdhci.3",
|
||||
.parent = &exynos5_clk_aclk_200.clk,
|
||||
.enable = exynos5_clk_ip_fsys_ctrl,
|
||||
.ctrlbit = (1 << 15),
|
||||
|
@ -813,7 +813,7 @@ static struct clksrc_clk exynos5_clk_sclk_uart3 = {
|
|||
static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
|
||||
.clk = {
|
||||
.name = "sclk_mmc",
|
||||
.devname = "s3c-sdhci.0",
|
||||
.devname = "exynos4-sdhci.0",
|
||||
.parent = &exynos5_clk_dout_mmc0.clk,
|
||||
.enable = exynos5_clksrc_mask_fsys_ctrl,
|
||||
.ctrlbit = (1 << 0),
|
||||
|
@ -824,7 +824,7 @@ static struct clksrc_clk exynos5_clk_sclk_mmc0 = {
|
|||
static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
|
||||
.clk = {
|
||||
.name = "sclk_mmc",
|
||||
.devname = "s3c-sdhci.1",
|
||||
.devname = "exynos4-sdhci.1",
|
||||
.parent = &exynos5_clk_dout_mmc1.clk,
|
||||
.enable = exynos5_clksrc_mask_fsys_ctrl,
|
||||
.ctrlbit = (1 << 4),
|
||||
|
@ -835,7 +835,7 @@ static struct clksrc_clk exynos5_clk_sclk_mmc1 = {
|
|||
static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
|
||||
.clk = {
|
||||
.name = "sclk_mmc",
|
||||
.devname = "s3c-sdhci.2",
|
||||
.devname = "exynos4-sdhci.2",
|
||||
.parent = &exynos5_clk_dout_mmc2.clk,
|
||||
.enable = exynos5_clksrc_mask_fsys_ctrl,
|
||||
.ctrlbit = (1 << 8),
|
||||
|
@ -846,7 +846,7 @@ static struct clksrc_clk exynos5_clk_sclk_mmc2 = {
|
|||
static struct clksrc_clk exynos5_clk_sclk_mmc3 = {
|
||||
.clk = {
|
||||
.name = "sclk_mmc",
|
||||
.devname = "s3c-sdhci.3",
|
||||
.devname = "exynos4-sdhci.3",
|
||||
.parent = &exynos5_clk_dout_mmc3.clk,
|
||||
.enable = exynos5_clksrc_mask_fsys_ctrl,
|
||||
.ctrlbit = (1 << 12),
|
||||
|
@ -990,10 +990,10 @@ static struct clk_lookup exynos5_clk_lookup[] = {
|
|||
CLKDEV_INIT("exynos4210-uart.1", "clk_uart_baud0", &exynos5_clk_sclk_uart1.clk),
|
||||
CLKDEV_INIT("exynos4210-uart.2", "clk_uart_baud0", &exynos5_clk_sclk_uart2.clk),
|
||||
CLKDEV_INIT("exynos4210-uart.3", "clk_uart_baud0", &exynos5_clk_sclk_uart3.clk),
|
||||
CLKDEV_INIT("s3c-sdhci.0", "mmc_busclk.2", &exynos5_clk_sclk_mmc0.clk),
|
||||
CLKDEV_INIT("s3c-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk),
|
||||
CLKDEV_INIT("s3c-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk),
|
||||
CLKDEV_INIT("s3c-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk),
|
||||
CLKDEV_INIT("exynos4-sdhci.0", "mmc_busclk.2", &exynos5_clk_sclk_mmc0.clk),
|
||||
CLKDEV_INIT("exynos4-sdhci.1", "mmc_busclk.2", &exynos5_clk_sclk_mmc1.clk),
|
||||
CLKDEV_INIT("exynos4-sdhci.2", "mmc_busclk.2", &exynos5_clk_sclk_mmc2.clk),
|
||||
CLKDEV_INIT("exynos4-sdhci.3", "mmc_busclk.2", &exynos5_clk_sclk_mmc3.clk),
|
||||
CLKDEV_INIT("dma-pl330.0", "apb_pclk", &exynos5_clk_pdma0),
|
||||
CLKDEV_INIT("dma-pl330.1", "apb_pclk", &exynos5_clk_pdma1),
|
||||
CLKDEV_INIT("dma-pl330.2", "apb_pclk", &exynos5_clk_mdma1),
|
||||
|
|
|
@ -326,6 +326,11 @@ static void __init exynos4_map_io(void)
|
|||
s3c_fimc_setname(2, "exynos4-fimc");
|
||||
s3c_fimc_setname(3, "exynos4-fimc");
|
||||
|
||||
s3c_sdhci_setname(0, "exynos4-sdhci");
|
||||
s3c_sdhci_setname(1, "exynos4-sdhci");
|
||||
s3c_sdhci_setname(2, "exynos4-sdhci");
|
||||
s3c_sdhci_setname(3, "exynos4-sdhci");
|
||||
|
||||
/* The I2C bus controllers are directly compatible with s3c2440 */
|
||||
s3c_i2c0_setname("s3c2440-i2c");
|
||||
s3c_i2c1_setname("s3c2440-i2c");
|
||||
|
@ -344,6 +349,11 @@ static void __init exynos5_map_io(void)
|
|||
s3c_device_i2c0.resource[1].start = EXYNOS5_IRQ_IIC;
|
||||
s3c_device_i2c0.resource[1].end = EXYNOS5_IRQ_IIC;
|
||||
|
||||
s3c_sdhci_setname(0, "exynos4-sdhci");
|
||||
s3c_sdhci_setname(1, "exynos4-sdhci");
|
||||
s3c_sdhci_setname(2, "exynos4-sdhci");
|
||||
s3c_sdhci_setname(3, "exynos4-sdhci");
|
||||
|
||||
/* The I2C bus controllers are directly compatible with s3c2440 */
|
||||
s3c_i2c0_setname("s3c2440-i2c");
|
||||
s3c_i2c1_setname("s3c2440-i2c");
|
||||
|
@ -537,7 +547,9 @@ void __init exynos5_init_irq(void)
|
|||
{
|
||||
int irq;
|
||||
|
||||
gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
|
||||
#ifdef CONFIG_OF
|
||||
of_irq_init(exynos4_dt_irq_match);
|
||||
#endif
|
||||
|
||||
for (irq = 0; irq < EXYNOS5_MAX_COMBINER_NR; irq++) {
|
||||
combiner_init(irq, (void __iomem *)S5P_VA_COMBINER(irq),
|
||||
|
|
|
@ -16,6 +16,7 @@
|
|||
#include <linux/dma-mapping.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/mmc/dw_mmc.h>
|
||||
|
||||
#include <plat/devs.h>
|
||||
|
@ -33,16 +34,8 @@ static int exynos4_dwmci_init(u32 slot_id, irq_handler_t handler, void *data)
|
|||
}
|
||||
|
||||
static struct resource exynos4_dwmci_resource[] = {
|
||||
[0] = {
|
||||
.start = EXYNOS4_PA_DWMCI,
|
||||
.end = EXYNOS4_PA_DWMCI + SZ_4K - 1,
|
||||
.flags = IORESOURCE_MEM,
|
||||
},
|
||||
[1] = {
|
||||
.start = IRQ_DWMCI,
|
||||
.end = IRQ_DWMCI,
|
||||
.flags = IORESOURCE_IRQ,
|
||||
}
|
||||
[0] = DEFINE_RES_MEM(EXYNOS4_PA_DWMCI, SZ_4K),
|
||||
[1] = DEFINE_RES_IRQ(EXYNOS4_IRQ_DWMCI),
|
||||
};
|
||||
|
||||
static struct dw_mci_board exynos4_dwci_pdata = {
|
||||
|
|
|
@ -112,6 +112,7 @@ static struct s3c_sdhci_platdata nuri_hsmmc0_data __initdata = {
|
|||
.host_caps = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
|
||||
MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED |
|
||||
MMC_CAP_ERASE),
|
||||
.host_caps2 = MMC_CAP2_BROKEN_VOLTAGE,
|
||||
.cd_type = S3C_SDHCI_CD_PERMANENT,
|
||||
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
|
||||
};
|
||||
|
|
|
@ -747,6 +747,7 @@ static struct s3c_sdhci_platdata universal_hsmmc0_data __initdata = {
|
|||
.max_width = 8,
|
||||
.host_caps = (MMC_CAP_8_BIT_DATA | MMC_CAP_4_BIT_DATA |
|
||||
MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
|
||||
.host_caps2 = MMC_CAP2_BROKEN_VOLTAGE,
|
||||
.cd_type = S3C_SDHCI_CD_PERMANENT,
|
||||
.clk_type = S3C_SDHCI_CLK_DIV_EXTERNAL,
|
||||
};
|
||||
|
|
|
@ -850,6 +850,8 @@ config SOC_IMX6Q
|
|||
select HAVE_IMX_MMDC
|
||||
select HAVE_IMX_SRC
|
||||
select HAVE_SMP
|
||||
select PINCTRL
|
||||
select PINCTRL_IMX6Q
|
||||
select USE_OF
|
||||
|
||||
help
|
||||
|
|
|
@ -14,6 +14,7 @@
|
|||
#include <linux/irqdomain.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/pinctrl/machine.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/time.h>
|
||||
#include <mach/common.h>
|
||||
|
@ -81,6 +82,8 @@ static void __init imx51_dt_init(void)
|
|||
|
||||
of_irq_init(imx51_irq_match);
|
||||
|
||||
pinctrl_provide_dummies();
|
||||
|
||||
node = of_find_matching_node(NULL, imx51_iomuxc_of_match);
|
||||
if (node) {
|
||||
of_id = of_match_node(imx51_iomuxc_of_match, node);
|
||||
|
|
|
@ -18,6 +18,7 @@
|
|||
#include <linux/irqdomain.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/pinctrl/machine.h>
|
||||
#include <asm/mach/arch.h>
|
||||
#include <asm/mach/time.h>
|
||||
#include <mach/common.h>
|
||||
|
@ -104,6 +105,8 @@ static void __init imx53_dt_init(void)
|
|||
|
||||
of_irq_init(imx53_irq_match);
|
||||
|
||||
pinctrl_provide_dummies();
|
||||
|
||||
node = of_find_matching_node(NULL, imx53_iomuxc_of_match);
|
||||
if (node) {
|
||||
of_id = of_match_node(imx53_iomuxc_of_match, node);
|
||||
|
|
|
@ -21,6 +21,7 @@
|
|||
#include <linux/of_address.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/pinctrl/machine.h>
|
||||
#include <linux/phy.h>
|
||||
#include <linux/micrel_phy.h>
|
||||
#include <asm/smp_twd.h>
|
||||
|
@ -114,6 +115,12 @@ static void __init imx6q_sabrelite_init(void)
|
|||
|
||||
static void __init imx6q_init_machine(void)
|
||||
{
|
||||
/*
|
||||
* This should be removed when all imx6q boards have pinctrl
|
||||
* states for devices defined in device tree.
|
||||
*/
|
||||
pinctrl_provide_dummies();
|
||||
|
||||
if (of_machine_is_compatible("fsl,imx6q-sabrelite"))
|
||||
imx6q_sabrelite_init();
|
||||
|
||||
|
|
|
@ -18,6 +18,7 @@
|
|||
#include <linux/kernel.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/pinctrl/machine.h>
|
||||
|
||||
#include <asm/mach/map.h>
|
||||
|
||||
|
@ -58,4 +59,5 @@ void __init imx1_soc_init(void)
|
|||
MX1_GPIO_INT_PORTC, 0);
|
||||
mxc_register_gpio("imx1-gpio", 3, MX1_GPIO4_BASE_ADDR, SZ_256,
|
||||
MX1_GPIO_INT_PORTD, 0);
|
||||
pinctrl_provide_dummies();
|
||||
}
|
||||
|
|
|
@ -20,6 +20,7 @@
|
|||
|
||||
#include <linux/mm.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/pinctrl/machine.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/common.h>
|
||||
#include <mach/devices-common.h>
|
||||
|
@ -88,6 +89,7 @@ void __init imx21_soc_init(void)
|
|||
mxc_register_gpio("imx21-gpio", 4, MX21_GPIO5_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
|
||||
mxc_register_gpio("imx21-gpio", 5, MX21_GPIO6_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0);
|
||||
|
||||
pinctrl_provide_dummies();
|
||||
imx_add_imx_dma();
|
||||
platform_device_register_simple("imx21-audmux", 0, imx21_audmux_res,
|
||||
ARRAY_SIZE(imx21_audmux_res));
|
||||
|
|
|
@ -19,6 +19,7 @@
|
|||
#include <linux/mm.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/pinctrl/machine.h>
|
||||
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/mach/map.h>
|
||||
|
@ -95,6 +96,7 @@ void __init imx25_soc_init(void)
|
|||
mxc_register_gpio("imx31-gpio", 2, MX25_GPIO3_BASE_ADDR, SZ_16K, MX25_INT_GPIO3, 0);
|
||||
mxc_register_gpio("imx31-gpio", 3, MX25_GPIO4_BASE_ADDR, SZ_16K, MX25_INT_GPIO4, 0);
|
||||
|
||||
pinctrl_provide_dummies();
|
||||
/* i.mx25 has the i.mx35 type sdma */
|
||||
imx_add_imx_sdma("imx35-sdma", MX25_SDMA_BASE_ADDR, MX25_INT_SDMA, &imx25_sdma_pdata);
|
||||
/* i.mx25 has the i.mx31 type audmux */
|
||||
|
|
|
@ -20,6 +20,7 @@
|
|||
|
||||
#include <linux/mm.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/pinctrl/machine.h>
|
||||
#include <mach/hardware.h>
|
||||
#include <mach/common.h>
|
||||
#include <mach/devices-common.h>
|
||||
|
@ -89,6 +90,7 @@ void __init imx27_soc_init(void)
|
|||
mxc_register_gpio("imx21-gpio", 4, MX27_GPIO5_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0);
|
||||
mxc_register_gpio("imx21-gpio", 5, MX27_GPIO6_BASE_ADDR, SZ_256, MX27_INT_GPIO, 0);
|
||||
|
||||
pinctrl_provide_dummies();
|
||||
imx_add_imx_dma();
|
||||
/* imx27 has the imx21 type audmux */
|
||||
platform_device_register_simple("imx21-audmux", 0, imx27_audmux_res,
|
||||
|
|
|
@ -19,6 +19,7 @@
|
|||
#include <linux/mm.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/pinctrl/machine.h>
|
||||
|
||||
#include <asm/pgtable.h>
|
||||
#include <asm/system_misc.h>
|
||||
|
@ -273,6 +274,7 @@ void __init imx35_soc_init(void)
|
|||
mxc_register_gpio("imx31-gpio", 1, MX35_GPIO2_BASE_ADDR, SZ_16K, MX35_INT_GPIO2, 0);
|
||||
mxc_register_gpio("imx31-gpio", 2, MX35_GPIO3_BASE_ADDR, SZ_16K, MX35_INT_GPIO3, 0);
|
||||
|
||||
pinctrl_provide_dummies();
|
||||
if (to_version == 1) {
|
||||
strncpy(imx35_sdma_pdata.fw_name, "sdma-imx35-to1.bin",
|
||||
strlen(imx35_sdma_pdata.fw_name));
|
||||
|
|
|
@ -14,6 +14,7 @@
|
|||
#include <linux/mm.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/pinctrl/machine.h>
|
||||
|
||||
#include <asm/system_misc.h>
|
||||
#include <asm/mach/map.h>
|
||||
|
@ -224,6 +225,7 @@ void __init imx53_soc_init(void)
|
|||
mxc_register_gpio("imx31-gpio", 5, MX53_GPIO6_BASE_ADDR, SZ_16K, MX53_INT_GPIO6_LOW, MX53_INT_GPIO6_HIGH);
|
||||
mxc_register_gpio("imx31-gpio", 6, MX53_GPIO7_BASE_ADDR, SZ_16K, MX53_INT_GPIO7_LOW, MX53_INT_GPIO7_HIGH);
|
||||
|
||||
pinctrl_provide_dummies();
|
||||
/* i.mx53 has the i.mx35 type sdma */
|
||||
imx_add_imx_sdma("imx35-sdma", MX53_SDMA_BASE_ADDR, MX53_INT_SDMA, &imx53_sdma_pdata);
|
||||
|
||||
|
|
|
@ -17,6 +17,7 @@
|
|||
#include <linux/irqdomain.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/memblock.h>
|
||||
|
||||
|
@ -49,10 +50,22 @@ static void __init msm8x60_map_io(void)
|
|||
msm_map_msm8x60_io();
|
||||
}
|
||||
|
||||
#ifdef CONFIG_OF
|
||||
static struct of_device_id msm_dt_gic_match[] __initdata = {
|
||||
{ .compatible = "qcom,msm-8660-qgic", .data = gic_of_init },
|
||||
{}
|
||||
};
|
||||
#endif
|
||||
|
||||
static void __init msm8x60_init_irq(void)
|
||||
{
|
||||
gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE,
|
||||
(void *)MSM_QGIC_CPU_BASE);
|
||||
if (!of_have_populated_dt())
|
||||
gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE,
|
||||
(void *)MSM_QGIC_CPU_BASE);
|
||||
#ifdef CONFIG_OF
|
||||
else
|
||||
of_irq_init(msm_dt_gic_match);
|
||||
#endif
|
||||
|
||||
/* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
|
||||
writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);
|
||||
|
@ -73,16 +86,8 @@ static struct of_dev_auxdata msm_auxdata_lookup[] __initdata = {
|
|||
{}
|
||||
};
|
||||
|
||||
static struct of_device_id msm_dt_gic_match[] __initdata = {
|
||||
{ .compatible = "qcom,msm-8660-qgic", },
|
||||
{}
|
||||
};
|
||||
|
||||
static void __init msm8x60_dt_init(void)
|
||||
{
|
||||
irq_domain_generate_simple(msm_dt_gic_match, MSM8X60_QGIC_DIST_PHYS,
|
||||
GIC_SPI_START);
|
||||
|
||||
if (of_machine_is_compatible("qcom,msm8660-surf")) {
|
||||
printk(KERN_INFO "Init surf UART registers\n");
|
||||
msm8x60_init_uart12dm();
|
||||
|
|
|
@ -9,11 +9,13 @@ config SOC_IMX23
|
|||
bool
|
||||
select CPU_ARM926T
|
||||
select HAVE_PWM
|
||||
select PINCTRL_IMX23
|
||||
|
||||
config SOC_IMX28
|
||||
bool
|
||||
select CPU_ARM926T
|
||||
select HAVE_PWM
|
||||
select PINCTRL_IMX28
|
||||
|
||||
comment "MXS platforms:"
|
||||
|
||||
|
|
|
@ -19,11 +19,13 @@ extern void mxs_timer_init(struct clk *, int);
|
|||
extern void mxs_restart(char, const char *);
|
||||
extern int mxs_saif_clkmux_select(unsigned int clkmux);
|
||||
|
||||
extern void mx23_soc_init(void);
|
||||
extern int mx23_register_gpios(void);
|
||||
extern int mx23_clocks_init(void);
|
||||
extern void mx23_map_io(void);
|
||||
extern void mx23_init_irq(void);
|
||||
|
||||
extern void mx28_soc_init(void);
|
||||
extern int mx28_register_gpios(void);
|
||||
extern int mx28_clocks_init(void);
|
||||
extern void mx28_map_io(void);
|
||||
|
|
|
@ -207,6 +207,8 @@ static int apx4devkit_phy_fixup(struct phy_device *phy)
|
|||
|
||||
static void __init apx4devkit_init(void)
|
||||
{
|
||||
mx28_soc_init();
|
||||
|
||||
mxs_iomux_setup_multiple_pads(apx4devkit_pads,
|
||||
ARRAY_SIZE(apx4devkit_pads));
|
||||
|
||||
|
|
|
@ -319,6 +319,8 @@ static struct mxs_mmc_platform_data m28evk_mmc_pdata[] __initdata = {
|
|||
|
||||
static void __init m28evk_init(void)
|
||||
{
|
||||
mx28_soc_init();
|
||||
|
||||
mxs_iomux_setup_multiple_pads(m28evk_pads, ARRAY_SIZE(m28evk_pads));
|
||||
|
||||
mx28_add_duart();
|
||||
|
|
|
@ -141,6 +141,8 @@ static void __init mx23evk_init(void)
|
|||
{
|
||||
int ret;
|
||||
|
||||
mx23_soc_init();
|
||||
|
||||
mxs_iomux_setup_multiple_pads(mx23evk_pads, ARRAY_SIZE(mx23evk_pads));
|
||||
|
||||
mx23_add_duart();
|
||||
|
|
|
@ -413,6 +413,8 @@ static void __init mx28evk_init(void)
|
|||
{
|
||||
int ret;
|
||||
|
||||
mx28_soc_init();
|
||||
|
||||
mxs_iomux_setup_multiple_pads(mx28evk_pads, ARRAY_SIZE(mx28evk_pads));
|
||||
|
||||
mx28_add_duart();
|
||||
|
|
|
@ -85,6 +85,8 @@ static void __init stmp378x_dvb_init(void)
|
|||
{
|
||||
int ret;
|
||||
|
||||
mx23_soc_init();
|
||||
|
||||
mxs_iomux_setup_multiple_pads(stmp378x_dvb_pads,
|
||||
ARRAY_SIZE(stmp378x_dvb_pads));
|
||||
|
||||
|
|
|
@ -146,6 +146,8 @@ static struct mxs_mmc_platform_data tx28_mmc0_pdata __initdata = {
|
|||
|
||||
static void __init tx28_stk5v3_init(void)
|
||||
{
|
||||
mx28_soc_init();
|
||||
|
||||
mxs_iomux_setup_multiple_pads(tx28_stk5v3_pads,
|
||||
ARRAY_SIZE(tx28_stk5v3_pads));
|
||||
|
||||
|
|
|
@ -13,6 +13,7 @@
|
|||
|
||||
#include <linux/mm.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/pinctrl/machine.h>
|
||||
|
||||
#include <asm/mach/map.h>
|
||||
|
||||
|
@ -61,3 +62,13 @@ void __init mx28_init_irq(void)
|
|||
{
|
||||
icoll_init_irq();
|
||||
}
|
||||
|
||||
void __init mx23_soc_init(void)
|
||||
{
|
||||
pinctrl_provide_dummies();
|
||||
}
|
||||
|
||||
void __init mx28_soc_init(void)
|
||||
{
|
||||
pinctrl_provide_dummies();
|
||||
}
|
||||
|
|
|
@ -17,6 +17,7 @@
|
|||
*
|
||||
* bit 23 - Input/Output (PXA2xx specific)
|
||||
* bit 24 - Wakeup Enable(PXA2xx specific)
|
||||
* bit 25 - Keep Output (PXA2xx specific)
|
||||
*/
|
||||
|
||||
#define MFP_DIR_IN (0x0 << 23)
|
||||
|
@ -25,6 +26,12 @@
|
|||
#define MFP_DIR(x) (((x) >> 23) & 0x1)
|
||||
|
||||
#define MFP_LPM_CAN_WAKEUP (0x1 << 24)
|
||||
|
||||
/*
|
||||
* MFP_LPM_KEEP_OUTPUT must be specified for pins that need to
|
||||
* retain their last output level (low or high).
|
||||
* Note: MFP_LPM_KEEP_OUTPUT has no effect on pins configured for input.
|
||||
*/
|
||||
#define MFP_LPM_KEEP_OUTPUT (0x1 << 25)
|
||||
|
||||
#define WAKEUP_ON_EDGE_RISE (MFP_LPM_CAN_WAKEUP | MFP_LPM_EDGE_RISE)
|
||||
|
|
|
@ -33,6 +33,8 @@
|
|||
#define BANK_OFF(n) (((n) < 3) ? (n) << 2 : 0x100 + (((n) - 3) << 2))
|
||||
#define GPLR(x) __REG2(0x40E00000, BANK_OFF((x) >> 5))
|
||||
#define GPDR(x) __REG2(0x40E00000, BANK_OFF((x) >> 5) + 0x0c)
|
||||
#define GPSR(x) __REG2(0x40E00000, BANK_OFF((x) >> 5) + 0x18)
|
||||
#define GPCR(x) __REG2(0x40E00000, BANK_OFF((x) >> 5) + 0x24)
|
||||
|
||||
#define PWER_WE35 (1 << 24)
|
||||
|
||||
|
@ -348,6 +350,7 @@ static inline void pxa27x_mfp_init(void) {}
|
|||
#ifdef CONFIG_PM
|
||||
static unsigned long saved_gafr[2][4];
|
||||
static unsigned long saved_gpdr[4];
|
||||
static unsigned long saved_gplr[4];
|
||||
static unsigned long saved_pgsr[4];
|
||||
|
||||
static int pxa2xx_mfp_suspend(void)
|
||||
|
@ -366,14 +369,26 @@ static int pxa2xx_mfp_suspend(void)
|
|||
}
|
||||
|
||||
for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++) {
|
||||
|
||||
saved_gafr[0][i] = GAFR_L(i);
|
||||
saved_gafr[1][i] = GAFR_U(i);
|
||||
saved_gpdr[i] = GPDR(i * 32);
|
||||
saved_gplr[i] = GPLR(i * 32);
|
||||
saved_pgsr[i] = PGSR(i);
|
||||
|
||||
GPDR(i * 32) = gpdr_lpm[i];
|
||||
GPSR(i * 32) = PGSR(i);
|
||||
GPCR(i * 32) = ~PGSR(i);
|
||||
}
|
||||
|
||||
/* set GPDR bits taking into account MFP_LPM_KEEP_OUTPUT */
|
||||
for (i = 0; i < pxa_last_gpio; i++) {
|
||||
if ((gpdr_lpm[gpio_to_bank(i)] & GPIO_bit(i)) ||
|
||||
((gpio_desc[i].config & MFP_LPM_KEEP_OUTPUT) &&
|
||||
(saved_gpdr[gpio_to_bank(i)] & GPIO_bit(i))))
|
||||
GPDR(i) |= GPIO_bit(i);
|
||||
else
|
||||
GPDR(i) &= ~GPIO_bit(i);
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@ -384,6 +399,8 @@ static void pxa2xx_mfp_resume(void)
|
|||
for (i = 0; i <= gpio_to_bank(pxa_last_gpio); i++) {
|
||||
GAFR_L(i) = saved_gafr[0][i];
|
||||
GAFR_U(i) = saved_gafr[1][i];
|
||||
GPSR(i * 32) = saved_gplr[i];
|
||||
GPCR(i * 32) = ~saved_gplr[i];
|
||||
GPDR(i * 32) = saved_gpdr[i];
|
||||
PGSR(i) = saved_pgsr[i];
|
||||
}
|
||||
|
|
|
@ -421,8 +421,11 @@ void __init pxa27x_set_i2c_power_info(struct i2c_pxa_platform_data *info)
|
|||
pxa_register_device(&pxa27x_device_i2c_power, info);
|
||||
}
|
||||
|
||||
static struct pxa_gpio_platform_data pxa27x_gpio_info __initdata = {
|
||||
.gpio_set_wake = gpio_set_wake,
|
||||
};
|
||||
|
||||
static struct platform_device *devices[] __initdata = {
|
||||
&pxa_device_gpio,
|
||||
&pxa27x_device_udc,
|
||||
&pxa_device_pmu,
|
||||
&pxa_device_i2s,
|
||||
|
@ -458,6 +461,7 @@ static int __init pxa27x_init(void)
|
|||
register_syscore_ops(&pxa2xx_mfp_syscore_ops);
|
||||
register_syscore_ops(&pxa2xx_clock_syscore_ops);
|
||||
|
||||
pxa_register_device(&pxa_device_gpio, &pxa27x_gpio_info);
|
||||
ret = platform_add_devices(devices, ARRAY_SIZE(devices));
|
||||
}
|
||||
|
||||
|
|
|
@ -111,10 +111,6 @@ config S3C24XX_SETUP_TS
|
|||
help
|
||||
Compile in platform device definition for Samsung TouchScreen.
|
||||
|
||||
# cpu-specific sections
|
||||
|
||||
if CPU_S3C2410
|
||||
|
||||
config S3C2410_DMA
|
||||
bool
|
||||
depends on S3C24XX_DMA && (CPU_S3C2410 || CPU_S3C2442)
|
||||
|
@ -127,6 +123,10 @@ config S3C2410_PM
|
|||
help
|
||||
Power Management code common to S3C2410 and better
|
||||
|
||||
# cpu-specific sections
|
||||
|
||||
if CPU_S3C2410
|
||||
|
||||
config S3C24XX_SIMTEC_NOR
|
||||
bool
|
||||
help
|
||||
|
|
|
@ -25,6 +25,7 @@
|
|||
#include <linux/gpio_keys.h>
|
||||
#include <linux/input.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/mmc/host.h>
|
||||
#include <linux/interrupt.h>
|
||||
|
||||
#include <asm/hardware/vic.h>
|
||||
|
@ -765,6 +766,7 @@ static void __init goni_pmic_init(void)
|
|||
/* MoviNAND */
|
||||
static struct s3c_sdhci_platdata goni_hsmmc0_data __initdata = {
|
||||
.max_width = 4,
|
||||
.host_caps2 = MMC_CAP2_BROKEN_VOLTAGE,
|
||||
.cd_type = S3C_SDHCI_CD_PERMANENT,
|
||||
};
|
||||
|
||||
|
|
|
@ -306,7 +306,7 @@ void sa11x0_register_irda(struct irda_platform_data *irda)
|
|||
}
|
||||
|
||||
static struct resource sa1100_rtc_resources[] = {
|
||||
DEFINE_RES_MEM(0x90010000, 0x9001003f),
|
||||
DEFINE_RES_MEM(0x90010000, 0x40),
|
||||
DEFINE_RES_IRQ_NAMED(IRQ_RTC1Hz, "rtc 1Hz"),
|
||||
DEFINE_RES_IRQ_NAMED(IRQ_RTCAlrm, "rtc alarm"),
|
||||
};
|
||||
|
|
|
@ -1667,8 +1667,10 @@ void __init u300_init_irq(void)
|
|||
|
||||
for (i = 0; i < U300_VIC_IRQS_END; i++)
|
||||
set_bit(i, (unsigned long *) &mask[0]);
|
||||
vic_init((void __iomem *) U300_INTCON0_VBASE, 0, mask[0], mask[0]);
|
||||
vic_init((void __iomem *) U300_INTCON1_VBASE, 32, mask[1], mask[1]);
|
||||
vic_init((void __iomem *) U300_INTCON0_VBASE, IRQ_U300_INTCON0_START,
|
||||
mask[0], mask[0]);
|
||||
vic_init((void __iomem *) U300_INTCON1_VBASE, IRQ_U300_INTCON1_START,
|
||||
mask[1], mask[1]);
|
||||
}
|
||||
|
||||
|
||||
|
|
|
@ -146,9 +146,6 @@ static struct ab3100_platform_data ab3100_plf_data = {
|
|||
.min_uV = 1800000,
|
||||
.max_uV = 1800000,
|
||||
.valid_modes_mask = REGULATOR_MODE_NORMAL,
|
||||
.valid_ops_mask =
|
||||
REGULATOR_CHANGE_VOLTAGE |
|
||||
REGULATOR_CHANGE_STATUS,
|
||||
.always_on = 1,
|
||||
.boot_on = 1,
|
||||
},
|
||||
|
@ -160,9 +157,6 @@ static struct ab3100_platform_data ab3100_plf_data = {
|
|||
.min_uV = 2500000,
|
||||
.max_uV = 2500000,
|
||||
.valid_modes_mask = REGULATOR_MODE_NORMAL,
|
||||
.valid_ops_mask =
|
||||
REGULATOR_CHANGE_VOLTAGE |
|
||||
REGULATOR_CHANGE_STATUS,
|
||||
.always_on = 1,
|
||||
.boot_on = 1,
|
||||
},
|
||||
|
@ -230,8 +224,7 @@ static struct ab3100_platform_data ab3100_plf_data = {
|
|||
.max_uV = 1800000,
|
||||
.valid_modes_mask = REGULATOR_MODE_NORMAL,
|
||||
.valid_ops_mask =
|
||||
REGULATOR_CHANGE_VOLTAGE |
|
||||
REGULATOR_CHANGE_STATUS,
|
||||
REGULATOR_CHANGE_VOLTAGE,
|
||||
.always_on = 1,
|
||||
.boot_on = 1,
|
||||
},
|
||||
|
|
|
@ -12,101 +12,101 @@
|
|||
#ifndef __MACH_IRQS_H
|
||||
#define __MACH_IRQS_H
|
||||
|
||||
#define IRQ_U300_INTCON0_START 0
|
||||
#define IRQ_U300_INTCON1_START 32
|
||||
#define IRQ_U300_INTCON0_START 1
|
||||
#define IRQ_U300_INTCON1_START 33
|
||||
/* These are on INTCON0 - 30 lines */
|
||||
#define IRQ_U300_IRQ0_EXT 0
|
||||
#define IRQ_U300_IRQ1_EXT 1
|
||||
#define IRQ_U300_DMA 2
|
||||
#define IRQ_U300_VIDEO_ENC_0 3
|
||||
#define IRQ_U300_VIDEO_ENC_1 4
|
||||
#define IRQ_U300_AAIF_RX 5
|
||||
#define IRQ_U300_AAIF_TX 6
|
||||
#define IRQ_U300_AAIF_VGPIO 7
|
||||
#define IRQ_U300_AAIF_WAKEUP 8
|
||||
#define IRQ_U300_PCM_I2S0_FRAME 9
|
||||
#define IRQ_U300_PCM_I2S0_FIFO 10
|
||||
#define IRQ_U300_PCM_I2S1_FRAME 11
|
||||
#define IRQ_U300_PCM_I2S1_FIFO 12
|
||||
#define IRQ_U300_XGAM_GAMCON 13
|
||||
#define IRQ_U300_XGAM_CDI 14
|
||||
#define IRQ_U300_XGAM_CDICON 15
|
||||
#define IRQ_U300_IRQ0_EXT 1
|
||||
#define IRQ_U300_IRQ1_EXT 2
|
||||
#define IRQ_U300_DMA 3
|
||||
#define IRQ_U300_VIDEO_ENC_0 4
|
||||
#define IRQ_U300_VIDEO_ENC_1 5
|
||||
#define IRQ_U300_AAIF_RX 6
|
||||
#define IRQ_U300_AAIF_TX 7
|
||||
#define IRQ_U300_AAIF_VGPIO 8
|
||||
#define IRQ_U300_AAIF_WAKEUP 9
|
||||
#define IRQ_U300_PCM_I2S0_FRAME 10
|
||||
#define IRQ_U300_PCM_I2S0_FIFO 11
|
||||
#define IRQ_U300_PCM_I2S1_FRAME 12
|
||||
#define IRQ_U300_PCM_I2S1_FIFO 13
|
||||
#define IRQ_U300_XGAM_GAMCON 14
|
||||
#define IRQ_U300_XGAM_CDI 15
|
||||
#define IRQ_U300_XGAM_CDICON 16
|
||||
#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)
|
||||
/* MMIACC not used on the DB3210 or DB3350 chips */
|
||||
#define IRQ_U300_XGAM_MMIACC 16
|
||||
#define IRQ_U300_XGAM_MMIACC 17
|
||||
#endif
|
||||
#define IRQ_U300_XGAM_PDI 17
|
||||
#define IRQ_U300_XGAM_PDICON 18
|
||||
#define IRQ_U300_XGAM_GAMEACC 19
|
||||
#define IRQ_U300_XGAM_MCIDCT 20
|
||||
#define IRQ_U300_APEX 21
|
||||
#define IRQ_U300_UART0 22
|
||||
#define IRQ_U300_SPI 23
|
||||
#define IRQ_U300_TIMER_APP_OS 24
|
||||
#define IRQ_U300_TIMER_APP_DD 25
|
||||
#define IRQ_U300_TIMER_APP_GP1 26
|
||||
#define IRQ_U300_TIMER_APP_GP2 27
|
||||
#define IRQ_U300_TIMER_OS 28
|
||||
#define IRQ_U300_TIMER_MS 29
|
||||
#define IRQ_U300_KEYPAD_KEYBF 30
|
||||
#define IRQ_U300_KEYPAD_KEYBR 31
|
||||
#define IRQ_U300_XGAM_PDI 18
|
||||
#define IRQ_U300_XGAM_PDICON 19
|
||||
#define IRQ_U300_XGAM_GAMEACC 20
|
||||
#define IRQ_U300_XGAM_MCIDCT 21
|
||||
#define IRQ_U300_APEX 22
|
||||
#define IRQ_U300_UART0 23
|
||||
#define IRQ_U300_SPI 24
|
||||
#define IRQ_U300_TIMER_APP_OS 25
|
||||
#define IRQ_U300_TIMER_APP_DD 26
|
||||
#define IRQ_U300_TIMER_APP_GP1 27
|
||||
#define IRQ_U300_TIMER_APP_GP2 28
|
||||
#define IRQ_U300_TIMER_OS 29
|
||||
#define IRQ_U300_TIMER_MS 30
|
||||
#define IRQ_U300_KEYPAD_KEYBF 31
|
||||
#define IRQ_U300_KEYPAD_KEYBR 32
|
||||
/* These are on INTCON1 - 32 lines */
|
||||
#define IRQ_U300_GPIO_PORT0 32
|
||||
#define IRQ_U300_GPIO_PORT1 33
|
||||
#define IRQ_U300_GPIO_PORT2 34
|
||||
#define IRQ_U300_GPIO_PORT0 33
|
||||
#define IRQ_U300_GPIO_PORT1 34
|
||||
#define IRQ_U300_GPIO_PORT2 35
|
||||
|
||||
#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330) || \
|
||||
defined(CONFIG_MACH_U300_BS335)
|
||||
/* These are for DB3150, DB3200 and DB3350 */
|
||||
#define IRQ_U300_WDOG 35
|
||||
#define IRQ_U300_EVHIST 36
|
||||
#define IRQ_U300_MSPRO 37
|
||||
#define IRQ_U300_MMCSD_MCIINTR0 38
|
||||
#define IRQ_U300_MMCSD_MCIINTR1 39
|
||||
#define IRQ_U300_I2C0 40
|
||||
#define IRQ_U300_I2C1 41
|
||||
#define IRQ_U300_RTC 42
|
||||
#define IRQ_U300_NFIF 43
|
||||
#define IRQ_U300_NFIF2 44
|
||||
#define IRQ_U300_WDOG 36
|
||||
#define IRQ_U300_EVHIST 37
|
||||
#define IRQ_U300_MSPRO 38
|
||||
#define IRQ_U300_MMCSD_MCIINTR0 39
|
||||
#define IRQ_U300_MMCSD_MCIINTR1 40
|
||||
#define IRQ_U300_I2C0 41
|
||||
#define IRQ_U300_I2C1 42
|
||||
#define IRQ_U300_RTC 43
|
||||
#define IRQ_U300_NFIF 44
|
||||
#define IRQ_U300_NFIF2 45
|
||||
#endif
|
||||
|
||||
/* DB3150 and DB3200 have only 45 IRQs */
|
||||
#if defined(CONFIG_MACH_U300_BS2X) || defined(CONFIG_MACH_U300_BS330)
|
||||
#define U300_VIC_IRQS_END 45
|
||||
#define U300_VIC_IRQS_END 46
|
||||
#endif
|
||||
|
||||
/* The DB3350-specific interrupt lines */
|
||||
#ifdef CONFIG_MACH_U300_BS335
|
||||
#define IRQ_U300_ISP_F0 45
|
||||
#define IRQ_U300_ISP_F1 46
|
||||
#define IRQ_U300_ISP_F2 47
|
||||
#define IRQ_U300_ISP_F3 48
|
||||
#define IRQ_U300_ISP_F4 49
|
||||
#define IRQ_U300_GPIO_PORT3 50
|
||||
#define IRQ_U300_SYSCON_PLL_LOCK 51
|
||||
#define IRQ_U300_UART1 52
|
||||
#define IRQ_U300_GPIO_PORT4 53
|
||||
#define IRQ_U300_GPIO_PORT5 54
|
||||
#define IRQ_U300_GPIO_PORT6 55
|
||||
#define U300_VIC_IRQS_END 56
|
||||
#define IRQ_U300_ISP_F0 46
|
||||
#define IRQ_U300_ISP_F1 47
|
||||
#define IRQ_U300_ISP_F2 48
|
||||
#define IRQ_U300_ISP_F3 49
|
||||
#define IRQ_U300_ISP_F4 50
|
||||
#define IRQ_U300_GPIO_PORT3 51
|
||||
#define IRQ_U300_SYSCON_PLL_LOCK 52
|
||||
#define IRQ_U300_UART1 53
|
||||
#define IRQ_U300_GPIO_PORT4 54
|
||||
#define IRQ_U300_GPIO_PORT5 55
|
||||
#define IRQ_U300_GPIO_PORT6 56
|
||||
#define U300_VIC_IRQS_END 57
|
||||
#endif
|
||||
|
||||
/* The DB3210-specific interrupt lines */
|
||||
#ifdef CONFIG_MACH_U300_BS365
|
||||
#define IRQ_U300_GPIO_PORT3 35
|
||||
#define IRQ_U300_GPIO_PORT4 36
|
||||
#define IRQ_U300_WDOG 37
|
||||
#define IRQ_U300_EVHIST 38
|
||||
#define IRQ_U300_MSPRO 39
|
||||
#define IRQ_U300_MMCSD_MCIINTR0 40
|
||||
#define IRQ_U300_MMCSD_MCIINTR1 41
|
||||
#define IRQ_U300_I2C0 42
|
||||
#define IRQ_U300_I2C1 43
|
||||
#define IRQ_U300_RTC 44
|
||||
#define IRQ_U300_NFIF 45
|
||||
#define IRQ_U300_NFIF2 46
|
||||
#define IRQ_U300_SYSCON_PLL_LOCK 47
|
||||
#define U300_VIC_IRQS_END 48
|
||||
#define IRQ_U300_GPIO_PORT3 36
|
||||
#define IRQ_U300_GPIO_PORT4 37
|
||||
#define IRQ_U300_WDOG 38
|
||||
#define IRQ_U300_EVHIST 39
|
||||
#define IRQ_U300_MSPRO 40
|
||||
#define IRQ_U300_MMCSD_MCIINTR0 41
|
||||
#define IRQ_U300_MMCSD_MCIINTR1 42
|
||||
#define IRQ_U300_I2C0 43
|
||||
#define IRQ_U300_I2C1 44
|
||||
#define IRQ_U300_RTC 45
|
||||
#define IRQ_U300_NFIF 46
|
||||
#define IRQ_U300_NFIF2 47
|
||||
#define IRQ_U300_SYSCON_PLL_LOCK 48
|
||||
#define U300_VIC_IRQS_END 49
|
||||
#endif
|
||||
|
||||
/* Maximum 8*7 GPIO lines */
|
||||
|
@ -117,6 +117,6 @@
|
|||
#define IRQ_U300_GPIO_END (U300_VIC_IRQS_END)
|
||||
#endif
|
||||
|
||||
#define NR_IRQS (IRQ_U300_GPIO_END)
|
||||
#define NR_IRQS (IRQ_U300_GPIO_END - IRQ_U300_INTCON0_START)
|
||||
|
||||
#endif
|
||||
|
|
|
@ -168,7 +168,7 @@ static ssize_t mbox_read_fifo(struct device *dev,
|
|||
return sprintf(buf, "0x%X\n", mbox_value);
|
||||
}
|
||||
|
||||
static DEVICE_ATTR(fifo, S_IWUGO | S_IRUGO, mbox_read_fifo, mbox_write_fifo);
|
||||
static DEVICE_ATTR(fifo, S_IWUSR | S_IRUGO, mbox_read_fifo, mbox_write_fifo);
|
||||
|
||||
static int mbox_show(struct seq_file *s, void *data)
|
||||
{
|
||||
|
|
|
@ -18,6 +18,8 @@
|
|||
#ifndef __PLAT_S3C_SDHCI_H
|
||||
#define __PLAT_S3C_SDHCI_H __FILE__
|
||||
|
||||
#include <plat/devs.h>
|
||||
|
||||
struct platform_device;
|
||||
struct mmc_host;
|
||||
struct mmc_card;
|
||||
|
@ -356,4 +358,30 @@ static inline void exynos4_default_sdhci3(void) { }
|
|||
|
||||
#endif /* CONFIG_EXYNOS4_SETUP_SDHCI */
|
||||
|
||||
static inline void s3c_sdhci_setname(int id, char *name)
|
||||
{
|
||||
switch (id) {
|
||||
#ifdef CONFIG_S3C_DEV_HSMMC
|
||||
case 0:
|
||||
s3c_device_hsmmc0.name = name;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_S3C_DEV_HSMMC1
|
||||
case 1:
|
||||
s3c_device_hsmmc1.name = name;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_S3C_DEV_HSMMC2
|
||||
case 2:
|
||||
s3c_device_hsmmc2.name = name;
|
||||
break;
|
||||
#endif
|
||||
#ifdef CONFIG_S3C_DEV_HSMMC3
|
||||
case 3:
|
||||
s3c_device_hsmmc3.name = name;
|
||||
break;
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
#endif /* __PLAT_S3C_SDHCI_H */
|
||||
|
|
|
@ -38,7 +38,7 @@ static struct platform_device rtc_device = {
|
|||
.name = "rtc-bfin",
|
||||
.id = -1,
|
||||
};
|
||||
#endif
|
||||
#endif /* CONFIG_RTC_DRV_BFIN */
|
||||
|
||||
#if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
|
||||
#ifdef CONFIG_SERIAL_BFIN_UART0
|
||||
|
@ -100,7 +100,7 @@ static struct platform_device bfin_uart0_device = {
|
|||
.platform_data = &bfin_uart0_peripherals, /* Passed to driver */
|
||||
},
|
||||
};
|
||||
#endif
|
||||
#endif /* CONFIG_SERIAL_BFIN_UART0 */
|
||||
#ifdef CONFIG_SERIAL_BFIN_UART1
|
||||
static struct resource bfin_uart1_resources[] = {
|
||||
{
|
||||
|
@ -148,7 +148,7 @@ static struct platform_device bfin_uart1_device = {
|
|||
.platform_data = &bfin_uart1_peripherals, /* Passed to driver */
|
||||
},
|
||||
};
|
||||
#endif
|
||||
#endif /* CONFIG_SERIAL_BFIN_UART1 */
|
||||
#ifdef CONFIG_SERIAL_BFIN_UART2
|
||||
static struct resource bfin_uart2_resources[] = {
|
||||
{
|
||||
|
@ -196,8 +196,8 @@ static struct platform_device bfin_uart2_device = {
|
|||
.platform_data = &bfin_uart2_peripherals, /* Passed to driver */
|
||||
},
|
||||
};
|
||||
#endif
|
||||
#endif
|
||||
#endif /* CONFIG_SERIAL_BFIN_UART2 */
|
||||
#endif /* CONFIG_SERIAL_BFIN */
|
||||
|
||||
#if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
|
||||
#ifdef CONFIG_BFIN_SIR0
|
||||
|
@ -224,7 +224,7 @@ static struct platform_device bfin_sir0_device = {
|
|||
.num_resources = ARRAY_SIZE(bfin_sir0_resources),
|
||||
.resource = bfin_sir0_resources,
|
||||
};
|
||||
#endif
|
||||
#endif /* CONFIG_BFIN_SIR0 */
|
||||
#ifdef CONFIG_BFIN_SIR1
|
||||
static struct resource bfin_sir1_resources[] = {
|
||||
{
|
||||
|
@ -249,7 +249,7 @@ static struct platform_device bfin_sir1_device = {
|
|||
.num_resources = ARRAY_SIZE(bfin_sir1_resources),
|
||||
.resource = bfin_sir1_resources,
|
||||
};
|
||||
#endif
|
||||
#endif /* CONFIG_BFIN_SIR1 */
|
||||
#ifdef CONFIG_BFIN_SIR2
|
||||
static struct resource bfin_sir2_resources[] = {
|
||||
{
|
||||
|
@ -274,8 +274,8 @@ static struct platform_device bfin_sir2_device = {
|
|||
.num_resources = ARRAY_SIZE(bfin_sir2_resources),
|
||||
.resource = bfin_sir2_resources,
|
||||
};
|
||||
#endif
|
||||
#endif
|
||||
#endif /* CONFIG_BFIN_SIR2 */
|
||||
#endif /* CONFIG_BFIN_SIR */
|
||||
|
||||
#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
|
||||
#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
|
||||
|
@ -311,7 +311,7 @@ static struct platform_device bfin_sport0_uart_device = {
|
|||
.platform_data = &bfin_sport0_peripherals, /* Passed to driver */
|
||||
},
|
||||
};
|
||||
#endif
|
||||
#endif /* CONFIG_SERIAL_BFIN_SPORT0_UART */
|
||||
#ifdef CONFIG_SERIAL_BFIN_SPORT1_UART
|
||||
static struct resource bfin_sport1_uart_resources[] = {
|
||||
{
|
||||
|
@ -345,7 +345,7 @@ static struct platform_device bfin_sport1_uart_device = {
|
|||
.platform_data = &bfin_sport1_peripherals, /* Passed to driver */
|
||||
},
|
||||
};
|
||||
#endif
|
||||
#endif /* CONFIG_SERIAL_BFIN_SPORT1_UART */
|
||||
#ifdef CONFIG_SERIAL_BFIN_SPORT2_UART
|
||||
static struct resource bfin_sport2_uart_resources[] = {
|
||||
{
|
||||
|
@ -379,7 +379,7 @@ static struct platform_device bfin_sport2_uart_device = {
|
|||
.platform_data = &bfin_sport2_peripherals, /* Passed to driver */
|
||||
},
|
||||
};
|
||||
#endif
|
||||
#endif /* CONFIG_SERIAL_BFIN_SPORT2_UART */
|
||||
#ifdef CONFIG_SERIAL_BFIN_SPORT3_UART
|
||||
static struct resource bfin_sport3_uart_resources[] = {
|
||||
{
|
||||
|
@ -413,8 +413,8 @@ static struct platform_device bfin_sport3_uart_device = {
|
|||
.platform_data = &bfin_sport3_peripherals, /* Passed to driver */
|
||||
},
|
||||
};
|
||||
#endif
|
||||
#endif
|
||||
#endif /* CONFIG_SERIAL_BFIN_SPORT3_UART */
|
||||
#endif /* CONFIG_SERIAL_BFIN_SPORT */
|
||||
|
||||
#if defined(CONFIG_CAN_BFIN) || defined(CONFIG_CAN_BFIN_MODULE)
|
||||
static unsigned short bfin_can_peripherals[] = {
|
||||
|
@ -452,7 +452,7 @@ static struct platform_device bfin_can_device = {
|
|||
.platform_data = &bfin_can_peripherals, /* Passed to driver */
|
||||
},
|
||||
};
|
||||
#endif
|
||||
#endif /* CONFIG_CAN_BFIN */
|
||||
|
||||
/*
|
||||
* USB-LAN EzExtender board
|
||||
|
@ -488,7 +488,7 @@ static struct platform_device smc91x_device = {
|
|||
.platform_data = &smc91x_info,
|
||||
},
|
||||
};
|
||||
#endif
|
||||
#endif /* CONFIG_SMC91X */
|
||||
|
||||
#if defined(CONFIG_SPI_BFIN5XX) || defined(CONFIG_SPI_BFIN5XX_MODULE)
|
||||
/* all SPI peripherals info goes here */
|
||||
|
@ -518,7 +518,8 @@ static struct flash_platform_data bfin_spi_flash_data = {
|
|||
static struct bfin5xx_spi_chip spi_flash_chip_info = {
|
||||
.enable_dma = 0, /* use dma transfer with this chip*/
|
||||
};
|
||||
#endif
|
||||
#endif /* CONFIG_MTD_M25P80 */
|
||||
#endif /* CONFIG_SPI_BFIN5XX */
|
||||
|
||||
#if defined(CONFIG_TOUCHSCREEN_AD7879) || defined(CONFIG_TOUCHSCREEN_AD7879_MODULE)
|
||||
#include <linux/spi/ad7879.h>
|
||||
|
@ -535,7 +536,7 @@ static const struct ad7879_platform_data bfin_ad7879_ts_info = {
|
|||
.gpio_export = 1, /* Export GPIO to gpiolib */
|
||||
.gpio_base = -1, /* Dynamic allocation */
|
||||
};
|
||||
#endif
|
||||
#endif /* CONFIG_TOUCHSCREEN_AD7879 */
|
||||
|
||||
#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
|
||||
#include <asm/bfin-lq035q1.h>
|
||||
|
@ -564,7 +565,7 @@ static struct platform_device bfin_lq035q1_device = {
|
|||
.platform_data = &bfin_lq035q1_data,
|
||||
},
|
||||
};
|
||||
#endif
|
||||
#endif /* CONFIG_FB_BFIN_LQ035Q1 */
|
||||
|
||||
static struct spi_board_info bf538_spi_board_info[] __initdata = {
|
||||
#if defined(CONFIG_MTD_M25P80) \
|
||||
|
@ -579,7 +580,7 @@ static struct spi_board_info bf538_spi_board_info[] __initdata = {
|
|||
.controller_data = &spi_flash_chip_info,
|
||||
.mode = SPI_MODE_3,
|
||||
},
|
||||
#endif
|
||||
#endif /* CONFIG_MTD_M25P80 */
|
||||
#if defined(CONFIG_TOUCHSCREEN_AD7879_SPI) || defined(CONFIG_TOUCHSCREEN_AD7879_SPI_MODULE)
|
||||
{
|
||||
.modalias = "ad7879",
|
||||
|
@ -590,7 +591,7 @@ static struct spi_board_info bf538_spi_board_info[] __initdata = {
|
|||
.chip_select = 1,
|
||||
.mode = SPI_CPHA | SPI_CPOL,
|
||||
},
|
||||
#endif
|
||||
#endif /* CONFIG_TOUCHSCREEN_AD7879_SPI */
|
||||
#if defined(CONFIG_FB_BFIN_LQ035Q1) || defined(CONFIG_FB_BFIN_LQ035Q1_MODULE)
|
||||
{
|
||||
.modalias = "bfin-lq035q1-spi",
|
||||
|
@ -599,7 +600,7 @@ static struct spi_board_info bf538_spi_board_info[] __initdata = {
|
|||
.chip_select = 2,
|
||||
.mode = SPI_CPHA | SPI_CPOL,
|
||||
},
|
||||
#endif
|
||||
#endif /* CONFIG_FB_BFIN_LQ035Q1 */
|
||||
#if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
|
||||
{
|
||||
.modalias = "spidev",
|
||||
|
@ -607,7 +608,7 @@ static struct spi_board_info bf538_spi_board_info[] __initdata = {
|
|||
.bus_num = 0,
|
||||
.chip_select = 1,
|
||||
},
|
||||
#endif
|
||||
#endif /* CONFIG_SPI_SPIDEV */
|
||||
};
|
||||
|
||||
/* SPI (0) */
|
||||
|
@ -716,8 +717,6 @@ static struct platform_device bf538_spi_master2 = {
|
|||
},
|
||||
};
|
||||
|
||||
#endif /* spi master and devices */
|
||||
|
||||
#if defined(CONFIG_I2C_BLACKFIN_TWI) || defined(CONFIG_I2C_BLACKFIN_TWI_MODULE)
|
||||
static struct resource bfin_twi0_resource[] = {
|
||||
[0] = {
|
||||
|
@ -759,8 +758,8 @@ static struct platform_device i2c_bfin_twi1_device = {
|
|||
.num_resources = ARRAY_SIZE(bfin_twi1_resource),
|
||||
.resource = bfin_twi1_resource,
|
||||
};
|
||||
#endif
|
||||
#endif
|
||||
#endif /* CONFIG_BF542 */
|
||||
#endif /* CONFIG_I2C_BLACKFIN_TWI */
|
||||
|
||||
#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
|
||||
#include <linux/gpio_keys.h>
|
||||
|
|
|
@ -22,6 +22,7 @@
|
|||
#include <linux/bootmem.h>
|
||||
#include <linux/genalloc.h>
|
||||
#include <asm/dma-mapping.h>
|
||||
#include <linux/module.h>
|
||||
|
||||
struct dma_map_ops *dma_ops;
|
||||
EXPORT_SYMBOL(dma_ops);
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* Process creation support for Hexagon
|
||||
*
|
||||
* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
|
||||
* Copyright (c) 2010-2012, Code Aurora Forum. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
|
@ -88,7 +88,7 @@ void (*idle_sleep)(void) = default_idle;
|
|||
void cpu_idle(void)
|
||||
{
|
||||
while (1) {
|
||||
tick_nohz_stop_sched_tick(1);
|
||||
tick_nohz_idle_enter();
|
||||
local_irq_disable();
|
||||
while (!need_resched()) {
|
||||
idle_sleep();
|
||||
|
@ -97,7 +97,7 @@ void cpu_idle(void)
|
|||
local_irq_disable();
|
||||
}
|
||||
local_irq_enable();
|
||||
tick_nohz_restart_sched_tick();
|
||||
tick_nohz_idle_exit();
|
||||
schedule();
|
||||
}
|
||||
}
|
||||
|
|
|
@ -28,6 +28,7 @@
|
|||
#include <linux/ptrace.h>
|
||||
#include <linux/regset.h>
|
||||
#include <linux/user.h>
|
||||
#include <linux/elf.h>
|
||||
|
||||
#include <asm/user.h>
|
||||
|
||||
|
|
|
@ -1,7 +1,7 @@
|
|||
/*
|
||||
* SMP support for Hexagon
|
||||
*
|
||||
* Copyright (c) 2010-2011, Code Aurora Forum. All rights reserved.
|
||||
* Copyright (c) 2010-2012, Code Aurora Forum. All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 and
|
||||
|
@ -28,6 +28,7 @@
|
|||
#include <linux/sched.h>
|
||||
#include <linux/smp.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/cpu.h>
|
||||
|
||||
#include <asm/time.h> /* timer_interrupt */
|
||||
#include <asm/hexagon_vm.h>
|
||||
|
@ -177,7 +178,12 @@ void __cpuinit start_secondary(void)
|
|||
|
||||
printk(KERN_INFO "%s cpu %d\n", __func__, current_thread_info()->cpu);
|
||||
|
||||
notify_cpu_starting(cpu);
|
||||
|
||||
ipi_call_lock();
|
||||
set_cpu_online(cpu, true);
|
||||
ipi_call_unlock();
|
||||
|
||||
local_irq_enable();
|
||||
|
||||
cpu_idle();
|
||||
|
|
|
@ -28,6 +28,7 @@
|
|||
#include <linux/of.h>
|
||||
#include <linux/of_address.h>
|
||||
#include <linux/of_irq.h>
|
||||
#include <linux/module.h>
|
||||
|
||||
#include <asm/timer-regs.h>
|
||||
#include <asm/hexagon_vm.h>
|
||||
|
|
|
@ -21,6 +21,7 @@
|
|||
#include <linux/err.h>
|
||||
#include <linux/mm.h>
|
||||
#include <linux/vmalloc.h>
|
||||
#include <linux/binfmts.h>
|
||||
|
||||
#include <asm/vdso.h>
|
||||
|
||||
|
|
43
arch/powerpc/boot/dts/fsl/pq3-mpic-message-B.dtsi
Normal file
43
arch/powerpc/boot/dts/fsl/pq3-mpic-message-B.dtsi
Normal file
|
@ -0,0 +1,43 @@
|
|||
/*
|
||||
* PQ3 MPIC Message (Group B) device tree stub [ controller @ offset 0x42400 ]
|
||||
*
|
||||
* Copyright 2012 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
message@42400 {
|
||||
compatible = "fsl,mpic-v3.1-msgr";
|
||||
reg = <0x42400 0x200>;
|
||||
interrupts = <
|
||||
0xb4 2 0 0
|
||||
0xb5 2 0 0
|
||||
0xb6 2 0 0
|
||||
0xb7 2 0 0>;
|
||||
};
|
|
@ -53,6 +53,16 @@ timer@41100 {
|
|||
3 0 3 0>;
|
||||
};
|
||||
|
||||
message@41400 {
|
||||
compatible = "fsl,mpic-v3.1-msgr";
|
||||
reg = <0x41400 0x200>;
|
||||
interrupts = <
|
||||
0xb0 2 0 0
|
||||
0xb1 2 0 0
|
||||
0xb2 2 0 0
|
||||
0xb3 2 0 0>;
|
||||
};
|
||||
|
||||
msi@41600 {
|
||||
compatible = "fsl,mpic-msi";
|
||||
reg = <0x41600 0x80>;
|
||||
|
|
|
@ -275,9 +275,6 @@ struct mpic
|
|||
unsigned int isu_mask;
|
||||
/* Number of sources */
|
||||
unsigned int num_sources;
|
||||
/* default senses array */
|
||||
unsigned char *senses;
|
||||
unsigned int senses_count;
|
||||
|
||||
/* vector numbers used for internal sources (ipi/timers) */
|
||||
unsigned int ipi_vecs[4];
|
||||
|
@ -415,21 +412,6 @@ extern struct mpic *mpic_alloc(struct device_node *node,
|
|||
extern void mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
|
||||
phys_addr_t phys_addr);
|
||||
|
||||
/* Set default sense codes
|
||||
*
|
||||
* @mpic: controller
|
||||
* @senses: array of sense codes
|
||||
* @count: size of above array
|
||||
*
|
||||
* Optionally provide an array (indexed on hardware interrupt numbers
|
||||
* for this MPIC) of default sense codes for the chip. Those are linux
|
||||
* sense codes IRQ_TYPE_*
|
||||
*
|
||||
* The driver gets ownership of the pointer, don't dispose of it or
|
||||
* anything like that. __init only.
|
||||
*/
|
||||
extern void mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count);
|
||||
|
||||
|
||||
/* Initialize the controller. After this has been called, none of the above
|
||||
* should be called again for this mpic
|
||||
|
|
|
@ -13,6 +13,7 @@
|
|||
|
||||
#include <linux/types.h>
|
||||
#include <linux/spinlock.h>
|
||||
#include <asm/smp.h>
|
||||
|
||||
struct mpic_msgr {
|
||||
u32 __iomem *base;
|
||||
|
|
|
@ -15,11 +15,6 @@
|
|||
#ifndef __ASM_POWERPC_REG_BOOKE_H__
|
||||
#define __ASM_POWERPC_REG_BOOKE_H__
|
||||
|
||||
#ifdef CONFIG_BOOKE_WDT
|
||||
extern u32 booke_wdt_enabled;
|
||||
extern u32 booke_wdt_period;
|
||||
#endif /* CONFIG_BOOKE_WDT */
|
||||
|
||||
/* Machine State Register (MSR) Fields */
|
||||
#define MSR_GS (1<<28) /* Guest state */
|
||||
#define MSR_UCLE (1<<26) /* User-mode cache lock enable */
|
||||
|
|
|
@ -150,6 +150,9 @@ notrace void __init machine_init(u64 dt_ptr)
|
|||
}
|
||||
|
||||
#ifdef CONFIG_BOOKE_WDT
|
||||
extern u32 booke_wdt_enabled;
|
||||
extern u32 booke_wdt_period;
|
||||
|
||||
/* Checks wdt=x and wdt_period=xx command-line option */
|
||||
notrace int __init early_parse_wdt(char *p)
|
||||
{
|
||||
|
|
|
@ -21,6 +21,12 @@ static struct of_device_id __initdata mpc85xx_common_ids[] = {
|
|||
{ .compatible = "fsl,qe", },
|
||||
{ .compatible = "fsl,cpm2", },
|
||||
{ .compatible = "fsl,srio", },
|
||||
/* So that the DMA channel nodes can be probed individually: */
|
||||
{ .compatible = "fsl,eloplus-dma", },
|
||||
/* For the PMC driver */
|
||||
{ .compatible = "fsl,mpc8548-guts", },
|
||||
/* Probably unnecessary? */
|
||||
{ .compatible = "gpio-leds", },
|
||||
{},
|
||||
};
|
||||
|
||||
|
|
|
@ -399,12 +399,6 @@ static int __init board_fixups(void)
|
|||
machine_arch_initcall(mpc8568_mds, board_fixups);
|
||||
machine_arch_initcall(mpc8569_mds, board_fixups);
|
||||
|
||||
static struct of_device_id mpc85xx_ids[] = {
|
||||
{ .compatible = "fsl,mpc8548-guts", },
|
||||
{ .compatible = "gpio-leds", },
|
||||
{},
|
||||
};
|
||||
|
||||
static int __init mpc85xx_publish_devices(void)
|
||||
{
|
||||
if (machine_is(mpc8568_mds))
|
||||
|
@ -412,10 +406,7 @@ static int __init mpc85xx_publish_devices(void)
|
|||
if (machine_is(mpc8569_mds))
|
||||
simple_gpiochip_init("fsl,mpc8569mds-bcsr-gpio");
|
||||
|
||||
mpc85xx_common_publish_devices();
|
||||
of_platform_bus_probe(NULL, mpc85xx_ids, NULL);
|
||||
|
||||
return 0;
|
||||
return mpc85xx_common_publish_devices();
|
||||
}
|
||||
|
||||
machine_device_initcall(mpc8568_mds, mpc85xx_publish_devices);
|
||||
|
|
|
@ -460,18 +460,7 @@ static void __init p1022_ds_setup_arch(void)
|
|||
pr_info("Freescale P1022 DS reference board\n");
|
||||
}
|
||||
|
||||
static struct of_device_id __initdata p1022_ds_ids[] = {
|
||||
/* So that the DMA channel nodes can be probed individually: */
|
||||
{ .compatible = "fsl,eloplus-dma", },
|
||||
{},
|
||||
};
|
||||
|
||||
static int __init p1022_ds_publish_devices(void)
|
||||
{
|
||||
mpc85xx_common_publish_devices();
|
||||
return of_platform_bus_probe(NULL, p1022_ds_ids, NULL);
|
||||
}
|
||||
machine_device_initcall(p1022_ds, p1022_ds_publish_devices);
|
||||
machine_device_initcall(p1022_ds, mpc85xx_common_publish_devices);
|
||||
|
||||
machine_arch_initcall(p1022_ds, swiotlb_setup_bus_notifier);
|
||||
|
||||
|
|
|
@ -366,11 +366,20 @@ static void kw_i2c_timeout(unsigned long data)
|
|||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&host->lock, flags);
|
||||
|
||||
/*
|
||||
* If the timer is pending, that means we raced with the
|
||||
* irq, in which case we just return
|
||||
*/
|
||||
if (timer_pending(&host->timeout_timer))
|
||||
goto skip;
|
||||
|
||||
kw_i2c_handle_interrupt(host, kw_read_reg(reg_isr));
|
||||
if (host->state != state_idle) {
|
||||
host->timeout_timer.expires = jiffies + KW_POLL_TIMEOUT;
|
||||
add_timer(&host->timeout_timer);
|
||||
}
|
||||
skip:
|
||||
spin_unlock_irqrestore(&host->lock, flags);
|
||||
}
|
||||
|
||||
|
|
|
@ -1076,7 +1076,7 @@ static void eeh_add_device_late(struct pci_dev *dev)
|
|||
pr_debug("EEH: Adding device %s\n", pci_name(dev));
|
||||
|
||||
dn = pci_device_to_OF_node(dev);
|
||||
edev = pci_dev_to_eeh_dev(dev);
|
||||
edev = of_node_to_eeh_dev(dn);
|
||||
if (edev->pdev == dev) {
|
||||
pr_debug("EEH: Already referenced !\n");
|
||||
return;
|
||||
|
|
|
@ -604,18 +604,14 @@ static struct mpic *mpic_find(unsigned int irq)
|
|||
}
|
||||
|
||||
/* Determine if the linux irq is an IPI */
|
||||
static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int irq)
|
||||
static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int src)
|
||||
{
|
||||
unsigned int src = virq_to_hw(irq);
|
||||
|
||||
return (src >= mpic->ipi_vecs[0] && src <= mpic->ipi_vecs[3]);
|
||||
}
|
||||
|
||||
/* Determine if the linux irq is a timer */
|
||||
static unsigned int mpic_is_tm(struct mpic *mpic, unsigned int irq)
|
||||
static unsigned int mpic_is_tm(struct mpic *mpic, unsigned int src)
|
||||
{
|
||||
unsigned int src = virq_to_hw(irq);
|
||||
|
||||
return (src >= mpic->timer_vecs[0] && src <= mpic->timer_vecs[7]);
|
||||
}
|
||||
|
||||
|
@ -876,21 +872,45 @@ int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type)
|
|||
if (src >= mpic->num_sources)
|
||||
return -EINVAL;
|
||||
|
||||
if (flow_type == IRQ_TYPE_NONE)
|
||||
if (mpic->senses && src < mpic->senses_count)
|
||||
flow_type = mpic->senses[src];
|
||||
if (flow_type == IRQ_TYPE_NONE)
|
||||
flow_type = IRQ_TYPE_LEVEL_LOW;
|
||||
vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
|
||||
|
||||
/* We don't support "none" type */
|
||||
if (flow_type == IRQ_TYPE_NONE)
|
||||
flow_type = IRQ_TYPE_DEFAULT;
|
||||
|
||||
/* Default: read HW settings */
|
||||
if (flow_type == IRQ_TYPE_DEFAULT) {
|
||||
switch(vold & (MPIC_INFO(VECPRI_POLARITY_MASK) |
|
||||
MPIC_INFO(VECPRI_SENSE_MASK))) {
|
||||
case MPIC_INFO(VECPRI_SENSE_EDGE) |
|
||||
MPIC_INFO(VECPRI_POLARITY_POSITIVE):
|
||||
flow_type = IRQ_TYPE_EDGE_RISING;
|
||||
break;
|
||||
case MPIC_INFO(VECPRI_SENSE_EDGE) |
|
||||
MPIC_INFO(VECPRI_POLARITY_NEGATIVE):
|
||||
flow_type = IRQ_TYPE_EDGE_FALLING;
|
||||
break;
|
||||
case MPIC_INFO(VECPRI_SENSE_LEVEL) |
|
||||
MPIC_INFO(VECPRI_POLARITY_POSITIVE):
|
||||
flow_type = IRQ_TYPE_LEVEL_HIGH;
|
||||
break;
|
||||
case MPIC_INFO(VECPRI_SENSE_LEVEL) |
|
||||
MPIC_INFO(VECPRI_POLARITY_NEGATIVE):
|
||||
flow_type = IRQ_TYPE_LEVEL_LOW;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* Apply to irq desc */
|
||||
irqd_set_trigger_type(d, flow_type);
|
||||
|
||||
/* Apply to HW */
|
||||
if (mpic_is_ht_interrupt(mpic, src))
|
||||
vecpri = MPIC_VECPRI_POLARITY_POSITIVE |
|
||||
MPIC_VECPRI_SENSE_EDGE;
|
||||
else
|
||||
vecpri = mpic_type_to_vecpri(mpic, flow_type);
|
||||
|
||||
vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
|
||||
vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) |
|
||||
MPIC_INFO(VECPRI_SENSE_MASK));
|
||||
vnew |= vecpri;
|
||||
|
@ -1026,7 +1046,7 @@ static int mpic_host_map(struct irq_domain *h, unsigned int virq,
|
|||
irq_set_chip_and_handler(virq, chip, handle_fasteoi_irq);
|
||||
|
||||
/* Set default irq type */
|
||||
irq_set_irq_type(virq, IRQ_TYPE_NONE);
|
||||
irq_set_irq_type(virq, IRQ_TYPE_DEFAULT);
|
||||
|
||||
/* If the MPIC was reset, then all vectors have already been
|
||||
* initialized. Otherwise, a per source lazy initialization
|
||||
|
@ -1417,12 +1437,6 @@ void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
|
|||
mpic->num_sources = isu_first + mpic->isu_size;
|
||||
}
|
||||
|
||||
void __init mpic_set_default_senses(struct mpic *mpic, u8 *senses, int count)
|
||||
{
|
||||
mpic->senses = senses;
|
||||
mpic->senses_count = count;
|
||||
}
|
||||
|
||||
void __init mpic_init(struct mpic *mpic)
|
||||
{
|
||||
int i, cpu;
|
||||
|
@ -1555,12 +1569,12 @@ void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
|
|||
return;
|
||||
|
||||
raw_spin_lock_irqsave(&mpic_lock, flags);
|
||||
if (mpic_is_ipi(mpic, irq)) {
|
||||
if (mpic_is_ipi(mpic, src)) {
|
||||
reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) &
|
||||
~MPIC_VECPRI_PRIORITY_MASK;
|
||||
mpic_ipi_write(src - mpic->ipi_vecs[0],
|
||||
reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
|
||||
} else if (mpic_is_tm(mpic, irq)) {
|
||||
} else if (mpic_is_tm(mpic, src)) {
|
||||
reg = mpic_tm_read(src - mpic->timer_vecs[0]) &
|
||||
~MPIC_VECPRI_PRIORITY_MASK;
|
||||
mpic_tm_write(src - mpic->timer_vecs[0],
|
||||
|
|
|
@ -27,6 +27,7 @@
|
|||
|
||||
static struct mpic_msgr **mpic_msgrs;
|
||||
static unsigned int mpic_msgr_count;
|
||||
static DEFINE_RAW_SPINLOCK(msgrs_lock);
|
||||
|
||||
static inline void _mpic_msgr_mer_write(struct mpic_msgr *msgr, u32 value)
|
||||
{
|
||||
|
@ -56,12 +57,11 @@ struct mpic_msgr *mpic_msgr_get(unsigned int reg_num)
|
|||
if (reg_num >= mpic_msgr_count)
|
||||
return ERR_PTR(-ENODEV);
|
||||
|
||||
raw_spin_lock_irqsave(&msgr->lock, flags);
|
||||
if (mpic_msgrs[reg_num]->in_use == MSGR_FREE) {
|
||||
msgr = mpic_msgrs[reg_num];
|
||||
raw_spin_lock_irqsave(&msgrs_lock, flags);
|
||||
msgr = mpic_msgrs[reg_num];
|
||||
if (msgr->in_use == MSGR_FREE)
|
||||
msgr->in_use = MSGR_INUSE;
|
||||
}
|
||||
raw_spin_unlock_irqrestore(&msgr->lock, flags);
|
||||
raw_spin_unlock_irqrestore(&msgrs_lock, flags);
|
||||
|
||||
return msgr;
|
||||
}
|
||||
|
@ -228,7 +228,7 @@ static __devinit int mpic_msgr_probe(struct platform_device *dev)
|
|||
|
||||
reg_number = block_number * MPIC_MSGR_REGISTERS_PER_BLOCK + i;
|
||||
msgr->base = msgr_block_addr + i * MPIC_MSGR_STRIDE;
|
||||
msgr->mer = msgr->base + MPIC_MSGR_MER_OFFSET;
|
||||
msgr->mer = (u32 *)((u8 *)msgr->base + MPIC_MSGR_MER_OFFSET);
|
||||
msgr->in_use = MSGR_FREE;
|
||||
msgr->num = i;
|
||||
raw_spin_lock_init(&msgr->lock);
|
||||
|
|
|
@ -22,6 +22,7 @@
|
|||
#include <linux/debugfs.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/export.h>
|
||||
#include <asm/debug.h>
|
||||
#include <asm/prom.h>
|
||||
#include <asm/scom.h>
|
||||
|
||||
|
|
|
@ -11,7 +11,7 @@
|
|||
#include <linux/types.h>
|
||||
#include <asm/cmpxchg.h>
|
||||
|
||||
#define ATOMIC_INIT(i) ( (atomic_t) { (i) } )
|
||||
#define ATOMIC_INIT(i) { (i) }
|
||||
|
||||
#define atomic_read(v) (*(volatile int *)&(v)->counter)
|
||||
#define atomic_set(v,i) ((v)->counter = (i))
|
||||
|
|
|
@ -86,7 +86,7 @@ static noinline int vmalloc_fault(unsigned long address)
|
|||
pte_t *pte_k;
|
||||
|
||||
/* Make sure we are in vmalloc/module/P3 area: */
|
||||
if (!(address >= VMALLOC_START && address < P3_ADDR_MAX))
|
||||
if (!(address >= P3SEG && address < P3_ADDR_MAX))
|
||||
return -1;
|
||||
|
||||
/*
|
||||
|
|
|
@ -47,8 +47,8 @@ struct pci_controller {
|
|||
*/
|
||||
#define PCI_DMA_BUS_IS_PHYS 1
|
||||
|
||||
int __devinit tile_pci_init(void);
|
||||
int __devinit pcibios_init(void);
|
||||
int __init tile_pci_init(void);
|
||||
int __init pcibios_init(void);
|
||||
|
||||
static inline void pci_iounmap(struct pci_dev *dev, void __iomem *addr) {}
|
||||
|
||||
|
|
|
@ -141,7 +141,7 @@ static int __devinit tile_init_irqs(int controller_id,
|
|||
*
|
||||
* Returns the number of controllers discovered.
|
||||
*/
|
||||
int __devinit tile_pci_init(void)
|
||||
int __init tile_pci_init(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
|
@ -287,7 +287,7 @@ static void __devinit fixup_read_and_payload_sizes(void)
|
|||
* The controllers have been set up by the time we get here, by a call to
|
||||
* tile_pci_init.
|
||||
*/
|
||||
int __devinit pcibios_init(void)
|
||||
int __init pcibios_init(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
|
|
|
@ -33,6 +33,9 @@
|
|||
__HEAD
|
||||
ENTRY(startup_32)
|
||||
#ifdef CONFIG_EFI_STUB
|
||||
jmp preferred_addr
|
||||
|
||||
.balign 0x10
|
||||
/*
|
||||
* We don't need the return address, so set up the stack so
|
||||
* efi_main() can find its arugments.
|
||||
|
@ -41,12 +44,17 @@ ENTRY(startup_32)
|
|||
|
||||
call efi_main
|
||||
cmpl $0, %eax
|
||||
je preferred_addr
|
||||
movl %eax, %esi
|
||||
call 1f
|
||||
jne 2f
|
||||
1:
|
||||
/* EFI init failed, so hang. */
|
||||
hlt
|
||||
jmp 1b
|
||||
2:
|
||||
call 3f
|
||||
3:
|
||||
popl %eax
|
||||
subl $1b, %eax
|
||||
subl $3b, %eax
|
||||
subl BP_pref_address(%esi), %eax
|
||||
add BP_code32_start(%esi), %eax
|
||||
leal preferred_addr(%eax), %eax
|
||||
|
|
|
@ -200,18 +200,28 @@ ENTRY(startup_64)
|
|||
* entire text+data+bss and hopefully all of memory.
|
||||
*/
|
||||
#ifdef CONFIG_EFI_STUB
|
||||
pushq %rsi
|
||||
/*
|
||||
* The entry point for the PE/COFF executable is 0x210, so only
|
||||
* legacy boot loaders will execute this jmp.
|
||||
*/
|
||||
jmp preferred_addr
|
||||
|
||||
.org 0x210
|
||||
mov %rcx, %rdi
|
||||
mov %rdx, %rsi
|
||||
call efi_main
|
||||
popq %rsi
|
||||
cmpq $0,%rax
|
||||
je preferred_addr
|
||||
movq %rax,%rsi
|
||||
call 1f
|
||||
cmpq $0,%rax
|
||||
jne 2f
|
||||
1:
|
||||
/* EFI init failed, so hang. */
|
||||
hlt
|
||||
jmp 1b
|
||||
2:
|
||||
call 3f
|
||||
3:
|
||||
popq %rax
|
||||
subq $1b, %rax
|
||||
subq $3b, %rax
|
||||
subq BP_pref_address(%rsi), %rax
|
||||
add BP_code32_start(%esi), %eax
|
||||
leaq preferred_addr(%rax), %rax
|
||||
|
|
|
@ -205,8 +205,13 @@ int main(int argc, char ** argv)
|
|||
put_unaligned_le32(file_sz, &buf[pe_header + 0x50]);
|
||||
|
||||
#ifdef CONFIG_X86_32
|
||||
/* Address of entry point */
|
||||
put_unaligned_le32(i, &buf[pe_header + 0x28]);
|
||||
/*
|
||||
* Address of entry point.
|
||||
*
|
||||
* The EFI stub entry point is +16 bytes from the start of
|
||||
* the .text section.
|
||||
*/
|
||||
put_unaligned_le32(i + 16, &buf[pe_header + 0x28]);
|
||||
|
||||
/* .text size */
|
||||
put_unaligned_le32(file_sz, &buf[pe_header + 0xb0]);
|
||||
|
@ -217,9 +222,11 @@ int main(int argc, char ** argv)
|
|||
/*
|
||||
* Address of entry point. startup_32 is at the beginning and
|
||||
* the 64-bit entry point (startup_64) is always 512 bytes
|
||||
* after.
|
||||
* after. The EFI stub entry point is 16 bytes after that, as
|
||||
* the first instruction allows legacy loaders to jump over
|
||||
* the EFI stub initialisation
|
||||
*/
|
||||
put_unaligned_le32(i + 512, &buf[pe_header + 0x28]);
|
||||
put_unaligned_le32(i + 528, &buf[pe_header + 0x28]);
|
||||
|
||||
/* .text size */
|
||||
put_unaligned_le32(file_sz, &buf[pe_header + 0xc0]);
|
||||
|
|
|
@ -7,9 +7,9 @@
|
|||
#else
|
||||
# ifdef __i386__
|
||||
# include "posix_types_32.h"
|
||||
# elif defined(__LP64__)
|
||||
# include "posix_types_64.h"
|
||||
# else
|
||||
# elif defined(__ILP32__)
|
||||
# include "posix_types_x32.h"
|
||||
# else
|
||||
# include "posix_types_64.h"
|
||||
# endif
|
||||
#endif
|
||||
|
|
|
@ -257,7 +257,7 @@ struct sigcontext {
|
|||
__u64 oldmask;
|
||||
__u64 cr2;
|
||||
struct _fpstate __user *fpstate; /* zero when no FPU context */
|
||||
#ifndef __LP64__
|
||||
#ifdef __ILP32__
|
||||
__u32 __fpstate_pad;
|
||||
#endif
|
||||
__u64 reserved1[8];
|
||||
|
|
|
@ -2,7 +2,13 @@
|
|||
#define _ASM_X86_SIGINFO_H
|
||||
|
||||
#ifdef __x86_64__
|
||||
# define __ARCH_SI_PREAMBLE_SIZE (4 * sizeof(int))
|
||||
# ifdef __ILP32__ /* x32 */
|
||||
typedef long long __kernel_si_clock_t __attribute__((aligned(4)));
|
||||
# define __ARCH_SI_CLOCK_T __kernel_si_clock_t
|
||||
# define __ARCH_SI_ATTRIBUTES __attribute__((aligned(8)))
|
||||
# else /* x86-64 */
|
||||
# define __ARCH_SI_PREAMBLE_SIZE (4 * sizeof(int))
|
||||
# endif
|
||||
#endif
|
||||
|
||||
#include <asm-generic/siginfo.h>
|
||||
|
|
|
@ -63,10 +63,10 @@
|
|||
#else
|
||||
# ifdef __i386__
|
||||
# include <asm/unistd_32.h>
|
||||
# elif defined(__LP64__)
|
||||
# include <asm/unistd_64.h>
|
||||
# else
|
||||
# elif defined(__ILP32__)
|
||||
# include <asm/unistd_x32.h>
|
||||
# else
|
||||
# include <asm/unistd_64.h>
|
||||
# endif
|
||||
#endif
|
||||
|
||||
|
|
|
@ -195,6 +195,5 @@ extern struct x86_msi_ops x86_msi;
|
|||
|
||||
extern void x86_init_noop(void);
|
||||
extern void x86_init_uint_noop(unsigned int unused);
|
||||
extern void x86_default_fixup_cpu_id(struct cpuinfo_x86 *c, int node);
|
||||
|
||||
#endif
|
||||
|
|
|
@ -24,6 +24,10 @@ unsigned long acpi_realmode_flags;
|
|||
static char temp_stack[4096];
|
||||
#endif
|
||||
|
||||
asmlinkage void acpi_enter_s3(void)
|
||||
{
|
||||
acpi_enter_sleep_state(3, wake_sleep_flags);
|
||||
}
|
||||
/**
|
||||
* acpi_suspend_lowlevel - save kernel state
|
||||
*
|
||||
|
|
|
@ -3,12 +3,16 @@
|
|||
*/
|
||||
|
||||
#include <asm/trampoline.h>
|
||||
#include <linux/linkage.h>
|
||||
|
||||
extern unsigned long saved_video_mode;
|
||||
extern long saved_magic;
|
||||
|
||||
extern int wakeup_pmode_return;
|
||||
|
||||
extern u8 wake_sleep_flags;
|
||||
extern asmlinkage void acpi_enter_s3(void);
|
||||
|
||||
extern unsigned long acpi_copy_wakeup_routine(unsigned long);
|
||||
extern void wakeup_long64(void);
|
||||
|
||||
|
|
|
@ -74,9 +74,7 @@ restore_registers:
|
|||
ENTRY(do_suspend_lowlevel)
|
||||
call save_processor_state
|
||||
call save_registers
|
||||
pushl $3
|
||||
call acpi_enter_sleep_state
|
||||
addl $4, %esp
|
||||
call acpi_enter_s3
|
||||
|
||||
# In case of S3 failure, we'll emerge here. Jump
|
||||
# to ret_point to recover
|
||||
|
|
|
@ -71,9 +71,7 @@ ENTRY(do_suspend_lowlevel)
|
|||
movq %rsi, saved_rsi
|
||||
|
||||
addq $8, %rsp
|
||||
movl $3, %edi
|
||||
xorl %eax, %eax
|
||||
call acpi_enter_sleep_state
|
||||
call acpi_enter_s3
|
||||
/* in case something went wrong, restore the machine status and go on */
|
||||
jmp resume_point
|
||||
|
||||
|
|
|
@ -1637,9 +1637,11 @@ static int __init apic_verify(void)
|
|||
mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
|
||||
|
||||
/* The BIOS may have set up the APIC at some other address */
|
||||
rdmsr(MSR_IA32_APICBASE, l, h);
|
||||
if (l & MSR_IA32_APICBASE_ENABLE)
|
||||
mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
|
||||
if (boot_cpu_data.x86 >= 6) {
|
||||
rdmsr(MSR_IA32_APICBASE, l, h);
|
||||
if (l & MSR_IA32_APICBASE_ENABLE)
|
||||
mp_lapic_addr = l & MSR_IA32_APICBASE_BASE;
|
||||
}
|
||||
|
||||
pr_info("Found and enabled local APIC!\n");
|
||||
return 0;
|
||||
|
@ -1657,13 +1659,15 @@ int __init apic_force_enable(unsigned long addr)
|
|||
* MSR. This can only be done in software for Intel P6 or later
|
||||
* and AMD K7 (Model > 1) or later.
|
||||
*/
|
||||
rdmsr(MSR_IA32_APICBASE, l, h);
|
||||
if (!(l & MSR_IA32_APICBASE_ENABLE)) {
|
||||
pr_info("Local APIC disabled by BIOS -- reenabling.\n");
|
||||
l &= ~MSR_IA32_APICBASE_BASE;
|
||||
l |= MSR_IA32_APICBASE_ENABLE | addr;
|
||||
wrmsr(MSR_IA32_APICBASE, l, h);
|
||||
enabled_via_apicbase = 1;
|
||||
if (boot_cpu_data.x86 >= 6) {
|
||||
rdmsr(MSR_IA32_APICBASE, l, h);
|
||||
if (!(l & MSR_IA32_APICBASE_ENABLE)) {
|
||||
pr_info("Local APIC disabled by BIOS -- reenabling.\n");
|
||||
l &= ~MSR_IA32_APICBASE_BASE;
|
||||
l |= MSR_IA32_APICBASE_ENABLE | addr;
|
||||
wrmsr(MSR_IA32_APICBASE, l, h);
|
||||
enabled_via_apicbase = 1;
|
||||
}
|
||||
}
|
||||
return apic_verify();
|
||||
}
|
||||
|
@ -2209,10 +2213,12 @@ static void lapic_resume(void)
|
|||
* FIXME! This will be wrong if we ever support suspend on
|
||||
* SMP! We'll need to do this as part of the CPU restore!
|
||||
*/
|
||||
rdmsr(MSR_IA32_APICBASE, l, h);
|
||||
l &= ~MSR_IA32_APICBASE_BASE;
|
||||
l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
|
||||
wrmsr(MSR_IA32_APICBASE, l, h);
|
||||
if (boot_cpu_data.x86 >= 6) {
|
||||
rdmsr(MSR_IA32_APICBASE, l, h);
|
||||
l &= ~MSR_IA32_APICBASE_BASE;
|
||||
l |= MSR_IA32_APICBASE_ENABLE | mp_lapic_addr;
|
||||
wrmsr(MSR_IA32_APICBASE, l, h);
|
||||
}
|
||||
}
|
||||
|
||||
maxlvt = lapic_get_maxlvt();
|
||||
|
|
|
@ -207,8 +207,11 @@ static void __init map_csrs(void)
|
|||
|
||||
static void fixup_cpu_id(struct cpuinfo_x86 *c, int node)
|
||||
{
|
||||
c->phys_proc_id = node;
|
||||
per_cpu(cpu_llc_id, smp_processor_id()) = node;
|
||||
|
||||
if (c->phys_proc_id != node) {
|
||||
c->phys_proc_id = node;
|
||||
per_cpu(cpu_llc_id, smp_processor_id()) = node;
|
||||
}
|
||||
}
|
||||
|
||||
static int __init numachip_system_init(void)
|
||||
|
|
|
@ -24,6 +24,12 @@ static int x2apic_acpi_madt_oem_check(char *oem_id, char *oem_table_id)
|
|||
{
|
||||
if (x2apic_phys)
|
||||
return x2apic_enabled();
|
||||
else if ((acpi_gbl_FADT.header.revision >= FADT2_REVISION_ID) &&
|
||||
(acpi_gbl_FADT.flags & ACPI_FADT_APIC_PHYSICAL) &&
|
||||
x2apic_enabled()) {
|
||||
printk(KERN_DEBUG "System requires x2apic physical mode\n");
|
||||
return 1;
|
||||
}
|
||||
else
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -26,7 +26,8 @@
|
|||
* contact AMD for precise details and a CPU swap.
|
||||
*
|
||||
* See http://www.multimania.com/poulot/k6bug.html
|
||||
* http://www.amd.com/K6/k6docs/revgd.html
|
||||
* and section 2.6.2 of "AMD-K6 Processor Revision Guide - Model 6"
|
||||
* (Publication # 21266 Issue Date: August 1998)
|
||||
*
|
||||
* The following test is erm.. interesting. AMD neglected to up
|
||||
* the chip setting when fixing the bug but they also tweaked some
|
||||
|
@ -94,7 +95,6 @@ static void __cpuinit init_amd_k6(struct cpuinfo_x86 *c)
|
|||
"system stability may be impaired when more than 32 MB are used.\n");
|
||||
else
|
||||
printk(KERN_CONT "probably OK (after B9730xxxx).\n");
|
||||
printk(KERN_INFO "Please see http://membres.lycos.fr/poulot/k6bug.html\n");
|
||||
}
|
||||
|
||||
/* K6 with old style WHCR */
|
||||
|
@ -353,10 +353,11 @@ static void __cpuinit srat_detect_node(struct cpuinfo_x86 *c)
|
|||
node = per_cpu(cpu_llc_id, cpu);
|
||||
|
||||
/*
|
||||
* If core numbers are inconsistent, it's likely a multi-fabric platform,
|
||||
* so invoke platform-specific handler
|
||||
* On multi-fabric platform (e.g. Numascale NumaChip) a
|
||||
* platform-specific handler needs to be called to fixup some
|
||||
* IDs of the CPU.
|
||||
*/
|
||||
if (c->phys_proc_id != node)
|
||||
if (x86_cpuinit.fixup_cpu_id)
|
||||
x86_cpuinit.fixup_cpu_id(c, node);
|
||||
|
||||
if (!node_online(node)) {
|
||||
|
|
|
@ -1162,15 +1162,6 @@ static void dbg_restore_debug_regs(void)
|
|||
#define dbg_restore_debug_regs()
|
||||
#endif /* ! CONFIG_KGDB */
|
||||
|
||||
/*
|
||||
* Prints an error where the NUMA and configured core-number mismatch and the
|
||||
* platform didn't override this to fix it up
|
||||
*/
|
||||
void __cpuinit x86_default_fixup_cpu_id(struct cpuinfo_x86 *c, int node)
|
||||
{
|
||||
pr_err("NUMA core number %d differs from configured core number %d\n", node, c->phys_proc_id);
|
||||
}
|
||||
|
||||
/*
|
||||
* cpu_init() initializes state that is per-CPU. Some data is already
|
||||
* initialized (naturally) in the bootstrap process, such as the GDT
|
||||
|
|
|
@ -433,14 +433,14 @@ int amd_set_l3_disable_slot(struct amd_northbridge *nb, int cpu, unsigned slot,
|
|||
/* check if @slot is already used or the index is already disabled */
|
||||
ret = amd_get_l3_disable_slot(nb, slot);
|
||||
if (ret >= 0)
|
||||
return -EINVAL;
|
||||
return -EEXIST;
|
||||
|
||||
if (index > nb->l3_cache.indices)
|
||||
return -EINVAL;
|
||||
|
||||
/* check whether the other slot has disabled the same index already */
|
||||
if (index == amd_get_l3_disable_slot(nb, !slot))
|
||||
return -EINVAL;
|
||||
return -EEXIST;
|
||||
|
||||
amd_l3_disable_index(nb, cpu, slot, index);
|
||||
|
||||
|
@ -468,8 +468,8 @@ static ssize_t store_cache_disable(struct _cpuid4_info *this_leaf,
|
|||
err = amd_set_l3_disable_slot(this_leaf->base.nb, cpu, slot, val);
|
||||
if (err) {
|
||||
if (err == -EEXIST)
|
||||
printk(KERN_WARNING "L3 disable slot %d in use!\n",
|
||||
slot);
|
||||
pr_warning("L3 slot %d in use/index already disabled!\n",
|
||||
slot);
|
||||
return err;
|
||||
}
|
||||
return count;
|
||||
|
|
|
@ -235,6 +235,7 @@ int init_fpu(struct task_struct *tsk)
|
|||
if (tsk_used_math(tsk)) {
|
||||
if (HAVE_HWFP && tsk == current)
|
||||
unlazy_fpu(tsk);
|
||||
tsk->thread.fpu.last_cpu = ~0;
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
@ -82,11 +82,6 @@ static int collect_cpu_info_amd(int cpu, struct cpu_signature *csig)
|
|||
{
|
||||
struct cpuinfo_x86 *c = &cpu_data(cpu);
|
||||
|
||||
if (c->x86_vendor != X86_VENDOR_AMD || c->x86 < 0x10) {
|
||||
pr_warning("CPU%d: family %d not supported\n", cpu, c->x86);
|
||||
return -1;
|
||||
}
|
||||
|
||||
csig->rev = c->microcode;
|
||||
pr_info("CPU%d: patch_level=0x%08x\n", cpu, csig->rev);
|
||||
|
||||
|
@ -380,6 +375,13 @@ static struct microcode_ops microcode_amd_ops = {
|
|||
|
||||
struct microcode_ops * __init init_amd_microcode(void)
|
||||
{
|
||||
struct cpuinfo_x86 *c = &cpu_data(0);
|
||||
|
||||
if (c->x86_vendor != X86_VENDOR_AMD || c->x86 < 0x10) {
|
||||
pr_warning("AMD CPU family 0x%x not supported\n", c->x86);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
patch = (void *)get_zeroed_page(GFP_KERNEL);
|
||||
if (!patch)
|
||||
return NULL;
|
||||
|
|
|
@ -419,10 +419,8 @@ static int mc_device_add(struct device *dev, struct subsys_interface *sif)
|
|||
if (err)
|
||||
return err;
|
||||
|
||||
if (microcode_init_cpu(cpu) == UCODE_ERROR) {
|
||||
sysfs_remove_group(&dev->kobj, &mc_attr_group);
|
||||
if (microcode_init_cpu(cpu) == UCODE_ERROR)
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return err;
|
||||
}
|
||||
|
@ -528,11 +526,11 @@ static int __init microcode_init(void)
|
|||
microcode_ops = init_intel_microcode();
|
||||
else if (c->x86_vendor == X86_VENDOR_AMD)
|
||||
microcode_ops = init_amd_microcode();
|
||||
|
||||
if (!microcode_ops) {
|
||||
else
|
||||
pr_err("no support for this CPU vendor\n");
|
||||
|
||||
if (!microcode_ops)
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
microcode_pdev = platform_device_register_simple("microcode", -1,
|
||||
NULL, 0);
|
||||
|
|
|
@ -93,7 +93,6 @@ struct x86_init_ops x86_init __initdata = {
|
|||
struct x86_cpuinit_ops x86_cpuinit __cpuinitdata = {
|
||||
.early_percpu_clock_init = x86_init_noop,
|
||||
.setup_percpu_clockev = setup_secondary_APIC_clock,
|
||||
.fixup_cpu_id = x86_default_fixup_cpu_id,
|
||||
};
|
||||
|
||||
static void default_nmi_init(void) { };
|
||||
|
|
|
@ -805,7 +805,7 @@ void intel_scu_devices_create(void)
|
|||
} else
|
||||
i2c_register_board_info(i2c_bus[i], i2c_devs[i], 1);
|
||||
}
|
||||
intel_scu_notifier_post(SCU_AVAILABLE, 0L);
|
||||
intel_scu_notifier_post(SCU_AVAILABLE, NULL);
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(intel_scu_devices_create);
|
||||
|
||||
|
@ -814,7 +814,7 @@ void intel_scu_devices_destroy(void)
|
|||
{
|
||||
int i;
|
||||
|
||||
intel_scu_notifier_post(SCU_DOWN, 0L);
|
||||
intel_scu_notifier_post(SCU_DOWN, NULL);
|
||||
|
||||
for (i = 0; i < ipc_next_dev; i++)
|
||||
platform_device_del(ipc_devs[i]);
|
||||
|
|
|
@ -261,7 +261,8 @@ static void xen_cpuid(unsigned int *ax, unsigned int *bx,
|
|||
|
||||
static bool __init xen_check_mwait(void)
|
||||
{
|
||||
#ifdef CONFIG_ACPI
|
||||
#if defined(CONFIG_ACPI) && !defined(CONFIG_ACPI_PROCESSOR_AGGREGATOR) && \
|
||||
!defined(CONFIG_ACPI_PROCESSOR_AGGREGATOR_MODULE)
|
||||
struct xen_platform_op op = {
|
||||
.cmd = XENPF_set_processor_pminfo,
|
||||
.u.set_pminfo.id = -1,
|
||||
|
@ -349,7 +350,6 @@ static void __init xen_init_cpuid_mask(void)
|
|||
/* Xen will set CR4.OSXSAVE if supported and not disabled by force */
|
||||
if ((cx & xsave_mask) != xsave_mask)
|
||||
cpuid_leaf1_ecx_mask &= ~xsave_mask; /* disable XSAVE & OSXSAVE */
|
||||
|
||||
if (xen_check_mwait())
|
||||
cpuid_leaf1_ecx_set_mask = (1 << (X86_FEATURE_MWAIT % 32));
|
||||
}
|
||||
|
|
|
@ -178,6 +178,7 @@ static void __init xen_fill_possible_map(void)
|
|||
static void __init xen_filter_cpu_maps(void)
|
||||
{
|
||||
int i, rc;
|
||||
unsigned int subtract = 0;
|
||||
|
||||
if (!xen_initial_domain())
|
||||
return;
|
||||
|
@ -192,8 +193,22 @@ static void __init xen_filter_cpu_maps(void)
|
|||
} else {
|
||||
set_cpu_possible(i, false);
|
||||
set_cpu_present(i, false);
|
||||
subtract++;
|
||||
}
|
||||
}
|
||||
#ifdef CONFIG_HOTPLUG_CPU
|
||||
/* This is akin to using 'nr_cpus' on the Linux command line.
|
||||
* Which is OK as when we use 'dom0_max_vcpus=X' we can only
|
||||
* have up to X, while nr_cpu_ids is greater than X. This
|
||||
* normally is not a problem, except when CPU hotplugging
|
||||
* is involved and then there might be more than X CPUs
|
||||
* in the guest - which will not work as there is no
|
||||
* hypercall to expand the max number of VCPUs an already
|
||||
* running guest has. So cap it up to X. */
|
||||
if (subtract)
|
||||
nr_cpu_ids = nr_cpu_ids - subtract;
|
||||
#endif
|
||||
|
||||
}
|
||||
|
||||
static void __init xen_smp_prepare_boot_cpu(void)
|
||||
|
|
|
@ -96,7 +96,7 @@ ENTRY(xen_restore_fl_direct)
|
|||
|
||||
/* check for unmasked and pending */
|
||||
cmpw $0x0001, PER_CPU_VAR(xen_vcpu_info) + XEN_vcpu_info_pending
|
||||
jz 1f
|
||||
jnz 1f
|
||||
2: call check_events
|
||||
1:
|
||||
ENDPATCH(xen_restore_fl_direct)
|
||||
|
|
|
@ -11,9 +11,6 @@
|
|||
#ifndef _XTENSA_HARDIRQ_H
|
||||
#define _XTENSA_HARDIRQ_H
|
||||
|
||||
void ack_bad_irq(unsigned int irq);
|
||||
#define ack_bad_irq ack_bad_irq
|
||||
|
||||
#include <asm-generic/hardirq.h>
|
||||
|
||||
#endif /* _XTENSA_HARDIRQ_H */
|
||||
|
|
|
@ -14,6 +14,7 @@
|
|||
#ifdef __KERNEL__
|
||||
#include <asm/byteorder.h>
|
||||
#include <asm/page.h>
|
||||
#include <linux/bug.h>
|
||||
#include <linux/kernel.h>
|
||||
|
||||
#include <linux/types.h>
|
||||
|
|
|
@ -496,6 +496,7 @@ int do_signal(struct pt_regs *regs, sigset_t *oldset)
|
|||
signr = get_signal_to_deliver(&info, &ka, regs, NULL);
|
||||
|
||||
if (signr > 0) {
|
||||
int ret;
|
||||
|
||||
/* Are we from a system call? */
|
||||
|
||||
|
|
Some files were not shown because too many files have changed in this diff Show more
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