drm/i915: Share crtc setup and teardown between dpms and disable/enable
This closes a couple of corner cases where we introduced and forgot about a couple of routines that need to be called when disabling the crtc and then re-enabling it. The code needs to be moved again so that the common bits are shared across generations. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
This commit is contained in:
Chris Wilson
parent
788319d48d
commit
6b383a7f63
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@ -44,7 +44,7 @@
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bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
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static void intel_update_watermarks(struct drm_device *dev);
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static void intel_increase_pllclock(struct drm_crtc *crtc);
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static void intel_crtc_update_cursor(struct drm_crtc *crtc);
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static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
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typedef struct {
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/* given values */
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@ -1927,6 +1927,26 @@ static void intel_flush_display_plane(struct drm_device *dev,
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I915_WRITE(reg, I915_READ(reg));
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}
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/*
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* When we disable a pipe, we need to clear any pending scanline wait events
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* to avoid hanging the ring, which we assume we are waiting on.
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*/
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static void intel_clear_scanline_wait(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 tmp;
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if (IS_GEN2(dev))
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/* Can't break the hang on i8xx */
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return;
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tmp = I915_READ(PRB0_CTL);
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if (tmp & RING_WAIT) {
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I915_WRITE(PRB0_CTL, tmp);
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POSTING_READ(PRB0_CTL);
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}
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}
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static void ironlake_crtc_enable(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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@ -1936,6 +1956,8 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
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int plane = intel_crtc->plane;
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u32 reg, temp;
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intel_update_watermarks(dev);
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if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
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temp = I915_READ(PCH_LVDS);
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if ((temp & LVDS_PORT_EN) == 0)
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@ -2082,6 +2104,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc)
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intel_crtc_load_lut(crtc);
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intel_update_fbc(dev);
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intel_crtc_update_cursor(crtc, true);
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}
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static void ironlake_crtc_disable(struct drm_crtc *crtc)
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@ -2094,6 +2117,7 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
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u32 reg, temp;
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drm_vblank_off(dev, pipe);
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intel_crtc_update_cursor(crtc, false);
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/* Disable display plane */
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reg = DSPCNTR(plane);
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@ -2220,6 +2244,10 @@ static void ironlake_crtc_disable(struct drm_crtc *crtc)
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/* Wait for the clocks to turn off. */
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POSTING_READ(reg);
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udelay(100);
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intel_update_watermarks(dev);
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intel_update_fbc(dev);
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intel_clear_scanline_wait(dev);
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}
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static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
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@ -2270,6 +2298,8 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
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int plane = intel_crtc->plane;
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u32 reg, temp;
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intel_update_watermarks(dev);
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/* Enable the DPLL */
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reg = DPLL(pipe);
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temp = I915_READ(reg);
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@ -2312,6 +2342,7 @@ static void i9xx_crtc_enable(struct drm_crtc *crtc)
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/* Give the overlay scaler a chance to enable if it's on this pipe */
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intel_crtc_dpms_overlay(intel_crtc, true);
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intel_crtc_update_cursor(crtc, true);
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}
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static void i9xx_crtc_disable(struct drm_crtc *crtc)
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@ -2325,6 +2356,7 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc)
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/* Give the overlay scaler a chance to disable if it's on this pipe */
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intel_crtc_dpms_overlay(intel_crtc, false);
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intel_crtc_update_cursor(crtc, false);
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drm_vblank_off(dev, pipe);
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if (dev_priv->cfb_plane == plane &&
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@ -2346,7 +2378,7 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc)
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/* Don't disable pipe A or pipe A PLLs if needed */
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if (pipe == 0 && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
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return;
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goto done;
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/* Next, disable display pipes */
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reg = PIPECONF(pipe);
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@ -2368,6 +2400,11 @@ static void i9xx_crtc_disable(struct drm_crtc *crtc)
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POSTING_READ(reg);
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udelay(150);
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}
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done:
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intel_update_fbc(dev);
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intel_update_watermarks(dev);
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intel_clear_scanline_wait(dev);
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}
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static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
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@ -2387,26 +2424,6 @@ static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
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}
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}
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/*
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* When we disable a pipe, we need to clear any pending scanline wait events
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* to avoid hanging the ring, which we assume we are waiting on.
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*/
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static void intel_clear_scanline_wait(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 tmp;
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if (IS_GEN2(dev))
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/* Can't break the hang on i8xx */
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return;
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tmp = I915_READ(PRB0_CTL);
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if (tmp & RING_WAIT) {
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I915_WRITE(PRB0_CTL, tmp);
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POSTING_READ(PRB0_CTL);
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}
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}
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/**
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* Sets the power management mode of the pipe and plane.
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*/
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@ -2423,34 +2440,9 @@ static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
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return;
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intel_crtc->dpms_mode = mode;
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intel_crtc->cursor_on = mode == DRM_MODE_DPMS_ON;
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/* When switching on the display, ensure that SR is disabled
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* with multiple pipes prior to enabling to new pipe.
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*
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* When switching off the display, make sure the cursor is
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* properly hidden and there are no pending waits prior to
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* disabling the pipe.
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*/
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if (mode == DRM_MODE_DPMS_ON)
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intel_update_watermarks(dev);
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else
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intel_crtc_update_cursor(crtc);
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dev_priv->display.dpms(crtc, mode);
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if (mode == DRM_MODE_DPMS_ON) {
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intel_crtc_update_cursor(crtc);
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} else {
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/* XXX Note that this is not a complete solution, but a hack
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* to avoid the most frequently hit hang.
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*/
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intel_clear_scanline_wait(dev);
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intel_update_watermarks(dev);
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}
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intel_update_fbc(dev);
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if (!dev->primary->master)
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return;
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@ -2485,50 +2477,22 @@ static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
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*/
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static void i9xx_crtc_prepare(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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intel_crtc->cursor_on = false;
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intel_crtc_update_cursor(crtc);
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i9xx_crtc_disable(crtc);
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intel_clear_scanline_wait(dev);
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}
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static void i9xx_crtc_commit(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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intel_update_watermarks(dev);
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i9xx_crtc_enable(crtc);
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intel_crtc->cursor_on = true;
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intel_crtc_update_cursor(crtc);
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}
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static void ironlake_crtc_prepare(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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intel_crtc->cursor_on = false;
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intel_crtc_update_cursor(crtc);
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ironlake_crtc_disable(crtc);
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intel_clear_scanline_wait(dev);
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}
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static void ironlake_crtc_commit(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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intel_update_watermarks(dev);
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ironlake_crtc_enable(crtc);
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intel_crtc->cursor_on = true;
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intel_crtc_update_cursor(crtc);
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}
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void intel_encoder_prepare (struct drm_encoder *encoder)
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@ -3615,7 +3579,7 @@ static int intel_crtc_mode_set(struct drm_crtc *crtc,
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}
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/* Ensure that the cursor is valid for the new mode before changing... */
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intel_crtc_update_cursor(crtc);
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intel_crtc_update_cursor(crtc, true);
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if (is_lvds && dev_priv->lvds_downclock_avail) {
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has_reduced_clock = limit->find_pll(limit, crtc,
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@ -4225,7 +4189,8 @@ static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
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}
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/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
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static void intel_crtc_update_cursor(struct drm_crtc *crtc)
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static void intel_crtc_update_cursor(struct drm_crtc *crtc,
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bool on)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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@ -4238,7 +4203,7 @@ static void intel_crtc_update_cursor(struct drm_crtc *crtc)
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pos = 0;
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if (intel_crtc->cursor_on && crtc->fb) {
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if (on && crtc->enabled && crtc->fb) {
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base = intel_crtc->cursor_addr;
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if (x > (int) crtc->fb->width)
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base = 0;
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@ -4370,7 +4335,7 @@ static int intel_crtc_cursor_set(struct drm_crtc *crtc,
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intel_crtc->cursor_width = width;
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intel_crtc->cursor_height = height;
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intel_crtc_update_cursor(crtc);
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intel_crtc_update_cursor(crtc, true);
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return 0;
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fail_unpin:
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@ -4389,7 +4354,7 @@ static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
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intel_crtc->cursor_x = x;
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intel_crtc->cursor_y = y;
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intel_crtc_update_cursor(crtc);
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intel_crtc_update_cursor(crtc, true);
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return 0;
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}
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@ -180,7 +180,7 @@ struct intel_crtc {
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uint32_t cursor_addr;
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int16_t cursor_x, cursor_y;
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int16_t cursor_width, cursor_height;
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bool cursor_visible, cursor_on;
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bool cursor_visible;
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};
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#define to_intel_crtc(x) container_of(x, struct intel_crtc, base)
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