drm/tilcdc: Remove obsolete crtc helper functions
Remove obsolete crtc helper functions. These are not needed when atomic modeset is used. Note that the drm_crtc_helper_funcs mode_fixup() is still needed. The crtc's check() callback can not do its job here. The plane's check() callback needs to set drm_crtc_state's ->mode_changed to true if the pixel format for the framebuffer changes. Because of this drm_mode_config_funcs atomic_check() callback needs to call drm_atomic_helper_check_modeset() once more after it has called drm_atomic_helper_check_planes(). If the fixing of the adjusted_mode would be done in drm_crtc_helper_funcs atomic_check() callback, it would get over written by the extra drm_atomic_helper_check_modeset() call. Signed-off-by: Jyri Sarha <jsarha@ti.com>
This commit is contained in:
Jyri Sarha
parent
305198de89
commit
6b4736db9c
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@ -501,209 +501,6 @@ static int tilcdc_crtc_atomic_check(struct drm_crtc *crtc,
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return 0;
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}
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static int tilcdc_crtc_mode_set(struct drm_crtc *crtc,
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struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode,
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int x, int y,
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struct drm_framebuffer *old_fb)
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{
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struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
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struct drm_device *dev = crtc->dev;
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struct tilcdc_drm_private *priv = dev->dev_private;
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const struct tilcdc_panel_info *info = tilcdc_crtc->info;
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uint32_t reg, hbp, hfp, hsw, vbp, vfp, vsw;
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int ret;
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ret = tilcdc_crtc_mode_valid(crtc, mode);
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if (WARN_ON(ret))
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return ret;
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if (WARN_ON(!info))
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return -EINVAL;
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ret = tilcdc_verify_fb(crtc, crtc->primary->fb);
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if (ret)
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return ret;
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pm_runtime_get_sync(dev->dev);
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/* Configure the Burst Size and fifo threshold of DMA: */
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reg = tilcdc_read(dev, LCDC_DMA_CTRL_REG) & ~0x00000770;
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switch (info->dma_burst_sz) {
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case 1:
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reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_1);
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break;
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case 2:
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reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_2);
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break;
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case 4:
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reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_4);
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break;
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case 8:
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reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_8);
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break;
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case 16:
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reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_16);
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break;
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default:
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return -EINVAL;
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}
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reg |= (info->fifo_th << 8);
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tilcdc_write(dev, LCDC_DMA_CTRL_REG, reg);
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/* Configure timings: */
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hbp = mode->htotal - mode->hsync_end;
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hfp = mode->hsync_start - mode->hdisplay;
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hsw = mode->hsync_end - mode->hsync_start;
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vbp = mode->vtotal - mode->vsync_end;
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vfp = mode->vsync_start - mode->vdisplay;
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vsw = mode->vsync_end - mode->vsync_start;
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DBG("%dx%d, hbp=%u, hfp=%u, hsw=%u, vbp=%u, vfp=%u, vsw=%u",
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mode->hdisplay, mode->vdisplay, hbp, hfp, hsw, vbp, vfp, vsw);
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/* Configure the AC Bias Period and Number of Transitions per Interrupt: */
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reg = tilcdc_read(dev, LCDC_RASTER_TIMING_2_REG) & ~0x000fff00;
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reg |= LCDC_AC_BIAS_FREQUENCY(info->ac_bias) |
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LCDC_AC_BIAS_TRANSITIONS_PER_INT(info->ac_bias_intrpt);
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/*
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* subtract one from hfp, hbp, hsw because the hardware uses
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* a value of 0 as 1
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*/
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if (priv->rev == 2) {
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/* clear bits we're going to set */
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reg &= ~0x78000033;
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reg |= ((hfp-1) & 0x300) >> 8;
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reg |= ((hbp-1) & 0x300) >> 4;
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reg |= ((hsw-1) & 0x3c0) << 21;
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}
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tilcdc_write(dev, LCDC_RASTER_TIMING_2_REG, reg);
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reg = (((mode->hdisplay >> 4) - 1) << 4) |
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(((hbp-1) & 0xff) << 24) |
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(((hfp-1) & 0xff) << 16) |
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(((hsw-1) & 0x3f) << 10);
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if (priv->rev == 2)
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reg |= (((mode->hdisplay >> 4) - 1) & 0x40) >> 3;
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tilcdc_write(dev, LCDC_RASTER_TIMING_0_REG, reg);
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reg = ((mode->vdisplay - 1) & 0x3ff) |
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((vbp & 0xff) << 24) |
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((vfp & 0xff) << 16) |
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(((vsw-1) & 0x3f) << 10);
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tilcdc_write(dev, LCDC_RASTER_TIMING_1_REG, reg);
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/*
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* be sure to set Bit 10 for the V2 LCDC controller,
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* otherwise limited to 1024 pixels width, stopping
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* 1920x1080 being suppoted.
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*/
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if (priv->rev == 2) {
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if ((mode->vdisplay - 1) & 0x400) {
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tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG,
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LCDC_LPP_B10);
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} else {
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tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG,
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LCDC_LPP_B10);
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}
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}
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/* Configure display type: */
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reg = tilcdc_read(dev, LCDC_RASTER_CTRL_REG) &
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~(LCDC_TFT_MODE | LCDC_MONO_8BIT_MODE | LCDC_MONOCHROME_MODE |
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LCDC_V2_TFT_24BPP_MODE | LCDC_V2_TFT_24BPP_UNPACK | 0x000ff000);
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reg |= LCDC_TFT_MODE; /* no monochrome/passive support */
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if (info->tft_alt_mode)
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reg |= LCDC_TFT_ALT_ENABLE;
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if (priv->rev == 2) {
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unsigned int depth, bpp;
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drm_fb_get_bpp_depth(crtc->primary->fb->pixel_format, &depth, &bpp);
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switch (bpp) {
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case 16:
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break;
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case 32:
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reg |= LCDC_V2_TFT_24BPP_UNPACK;
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/* fallthrough */
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case 24:
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reg |= LCDC_V2_TFT_24BPP_MODE;
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break;
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default:
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dev_err(dev->dev, "invalid pixel format\n");
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return -EINVAL;
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}
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}
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reg |= info->fdd < 12;
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tilcdc_write(dev, LCDC_RASTER_CTRL_REG, reg);
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if (info->invert_pxl_clk)
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tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK);
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else
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tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK);
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if (info->sync_ctrl)
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tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL);
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else
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tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL);
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if (info->sync_edge)
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tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE);
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else
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tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE);
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/*
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* use value from adjusted_mode here as this might have been
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* changed as part of the fixup for slave encoders to solve the
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* issue where tilcdc timings are not VESA compliant
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*/
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if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
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tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC);
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else
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tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC);
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if (mode->flags & DRM_MODE_FLAG_NVSYNC)
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tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC);
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else
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tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC);
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if (info->raster_order)
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tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER);
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else
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tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER);
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drm_framebuffer_reference(crtc->primary->fb);
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set_scanout(crtc, crtc->primary->fb);
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tilcdc_crtc_update_clk(crtc);
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pm_runtime_put_sync(dev->dev);
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return 0;
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}
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static int tilcdc_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
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struct drm_framebuffer *old_fb)
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{
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struct drm_device *dev = crtc->dev;
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int r;
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r = tilcdc_verify_fb(crtc, crtc->primary->fb);
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if (r)
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return r;
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drm_framebuffer_reference(crtc->primary->fb);
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pm_runtime_get_sync(dev->dev);
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set_scanout(crtc, crtc->primary->fb);
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pm_runtime_put_sync(dev->dev);
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return 0;
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}
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static const struct drm_crtc_funcs tilcdc_crtc_funcs = {
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.destroy = tilcdc_crtc_destroy,
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.set_config = drm_atomic_helper_set_config,
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@ -714,12 +511,7 @@ static const struct drm_crtc_funcs tilcdc_crtc_funcs = {
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};
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static const struct drm_crtc_helper_funcs tilcdc_crtc_helper_funcs = {
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.dpms = tilcdc_crtc_dpms,
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.mode_fixup = tilcdc_crtc_mode_fixup,
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.prepare = tilcdc_crtc_disable,
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.commit = tilcdc_crtc_enable,
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.mode_set = tilcdc_crtc_mode_set,
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.mode_set_base = tilcdc_crtc_mode_set_base,
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.enable = tilcdc_crtc_enable,
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.disable = tilcdc_crtc_disable,
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.atomic_check = tilcdc_crtc_atomic_check,
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