soc/tegra: pmc: Use BIT macro for register field definition
Use BIT macro for register field definition and make constant as U when using in shift operator like (3 << 30) to (3U << 30) Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
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@ -45,29 +45,29 @@
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#include <soc/tegra/pmc.h>
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#define PMC_CNTRL 0x0
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#define PMC_CNTRL_SYSCLK_POLARITY (1 << 10) /* sys clk polarity */
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#define PMC_CNTRL_SYSCLK_OE (1 << 11) /* system clock enable */
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#define PMC_CNTRL_SIDE_EFFECT_LP0 (1 << 14) /* LP0 when CPU pwr gated */
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#define PMC_CNTRL_CPU_PWRREQ_POLARITY (1 << 15) /* CPU pwr req polarity */
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#define PMC_CNTRL_CPU_PWRREQ_OE (1 << 16) /* CPU pwr req enable */
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#define PMC_CNTRL_INTR_POLARITY (1 << 17) /* inverts INTR polarity */
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#define PMC_CNTRL_MAIN_RST (1 << 4)
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#define PMC_CNTRL_MAIN_RST BIT(4)
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#define PMC_CNTRL_SYSCLK_POLARITY BIT(10) /* sys clk polarity */
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#define PMC_CNTRL_SYSCLK_OE BIT(11) /* system clock enable */
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#define PMC_CNTRL_SIDE_EFFECT_LP0 BIT(14) /* LP0 when CPU pwr gated */
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#define PMC_CNTRL_CPU_PWRREQ_POLARITY BIT(15) /* CPU pwr req polarity */
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#define PMC_CNTRL_CPU_PWRREQ_OE BIT(16) /* CPU pwr req enable */
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#define PMC_CNTRL_INTR_POLARITY BIT(17) /* inverts INTR polarity */
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#define DPD_SAMPLE 0x020
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#define DPD_SAMPLE_ENABLE (1 << 0)
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#define DPD_SAMPLE_ENABLE BIT(0)
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#define DPD_SAMPLE_DISABLE (0 << 0)
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#define PWRGATE_TOGGLE 0x30
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#define PWRGATE_TOGGLE_START (1 << 8)
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#define PWRGATE_TOGGLE_START BIT(8)
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#define REMOVE_CLAMPING 0x34
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#define PWRGATE_STATUS 0x38
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#define PMC_SCRATCH0 0x50
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#define PMC_SCRATCH0_MODE_RECOVERY (1 << 31)
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#define PMC_SCRATCH0_MODE_BOOTLOADER (1 << 30)
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#define PMC_SCRATCH0_MODE_RCM (1 << 1)
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#define PMC_SCRATCH0_MODE_RECOVERY BIT(31)
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#define PMC_SCRATCH0_MODE_BOOTLOADER BIT(30)
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#define PMC_SCRATCH0_MODE_RCM BIT(1)
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#define PMC_SCRATCH0_MODE_MASK (PMC_SCRATCH0_MODE_RECOVERY | \
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PMC_SCRATCH0_MODE_BOOTLOADER | \
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PMC_SCRATCH0_MODE_RCM)
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@ -78,8 +78,8 @@
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#define PMC_SCRATCH41 0x140
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#define PMC_SENSOR_CTRL 0x1b0
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#define PMC_SENSOR_CTRL_SCRATCH_WRITE (1 << 2)
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#define PMC_SENSOR_CTRL_ENABLE_RST (1 << 1)
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#define PMC_SENSOR_CTRL_SCRATCH_WRITE BIT(2)
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#define PMC_SENSOR_CTRL_ENABLE_RST BIT(1)
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#define PMC_RST_STATUS 0x1b4
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#define PMC_RST_STATUS_POR 0
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@ -90,10 +90,10 @@
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#define PMC_RST_STATUS_AOTAG 5
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#define IO_DPD_REQ 0x1b8
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#define IO_DPD_REQ_CODE_IDLE (0 << 30)
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#define IO_DPD_REQ_CODE_OFF (1 << 30)
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#define IO_DPD_REQ_CODE_ON (2 << 30)
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#define IO_DPD_REQ_CODE_MASK (3 << 30)
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#define IO_DPD_REQ_CODE_IDLE (0U << 30)
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#define IO_DPD_REQ_CODE_OFF (1U << 30)
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#define IO_DPD_REQ_CODE_ON (2U << 30)
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#define IO_DPD_REQ_CODE_MASK (3U << 30)
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#define IO_DPD_STATUS 0x1bc
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#define IO_DPD2_REQ 0x1c0
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@ -105,10 +105,10 @@
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#define PMC_SCRATCH54_ADDR_SHIFT 0
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#define PMC_SCRATCH55 0x25c
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#define PMC_SCRATCH55_RESET_TEGRA (1 << 31)
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#define PMC_SCRATCH55_RESET_TEGRA BIT(31)
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#define PMC_SCRATCH55_CNTRL_ID_SHIFT 27
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#define PMC_SCRATCH55_PINMUX_SHIFT 24
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#define PMC_SCRATCH55_16BITOP (1 << 15)
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#define PMC_SCRATCH55_16BITOP BIT(15)
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#define PMC_SCRATCH55_CHECKSUM_SHIFT 16
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#define PMC_SCRATCH55_I2CSLV1_SHIFT 0
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