ntb: intel: change references of skx to gen3
Change all references to skx to gen3 NTB. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>hifive-unleashed-5.1
Dave Jiang
Jon Mason
parent
f6e51c354b
commit
6c1e8ab2d1
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@ -45,9 +45,6 @@
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Intel PCIe NTB Linux driver
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*
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* Contact Information:
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* Jon Mason <jon.mason@intel.com>
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*/
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#include <linux/debugfs.h>
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@ -651,7 +648,7 @@ static ssize_t ndev_ntb_debugfs_read(struct file *filp, char __user *ubuf,
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"LMT45 -\t\t\t%#018llx\n", u.v64);
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}
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if (pdev_is_xeon(pdev)) {
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if (pdev_is_gen1(pdev)) {
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if (ntb_topo_is_b2b(ndev->ntb.topo)) {
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off += scnprintf(buf + off, buf_size - off,
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"\nNTB Outgoing B2B XLAT:\n");
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@ -763,9 +760,9 @@ static ssize_t ndev_debugfs_read(struct file *filp, char __user *ubuf,
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{
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struct intel_ntb_dev *ndev = filp->private_data;
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if (pdev_is_xeon(ndev->ntb.pdev))
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if (pdev_is_gen1(ndev->ntb.pdev))
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return ndev_ntb_debugfs_read(filp, ubuf, count, offp);
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else if (pdev_is_skx_xeon(ndev->ntb.pdev))
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else if (pdev_is_gen3(ndev->ntb.pdev))
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return ndev_ntb3_debugfs_read(filp, ubuf, count, offp);
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return -ENXIO;
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@ -1849,7 +1846,7 @@ static int intel_ntb_pci_probe(struct pci_dev *pdev,
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node = dev_to_node(&pdev->dev);
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if (pdev_is_xeon(pdev)) {
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if (pdev_is_gen1(pdev)) {
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ndev = kzalloc_node(sizeof(*ndev), GFP_KERNEL, node);
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if (!ndev) {
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rc = -ENOMEM;
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@ -1866,7 +1863,7 @@ static int intel_ntb_pci_probe(struct pci_dev *pdev,
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if (rc)
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goto err_init_dev;
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} else if (pdev_is_skx_xeon(pdev)) {
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} else if (pdev_is_gen3(pdev)) {
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ndev = kzalloc_node(sizeof(*ndev), GFP_KERNEL, node);
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if (!ndev) {
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rc = -ENOMEM;
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@ -1880,7 +1877,7 @@ static int intel_ntb_pci_probe(struct pci_dev *pdev,
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if (rc)
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goto err_init_pci;
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rc = skx_init_dev(ndev);
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rc = gen3_init_dev(ndev);
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if (rc)
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goto err_init_dev;
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@ -1905,7 +1902,7 @@ static int intel_ntb_pci_probe(struct pci_dev *pdev,
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err_register:
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ndev_deinit_debugfs(ndev);
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if (pdev_is_xeon(pdev) || pdev_is_skx_xeon(pdev))
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if (pdev_is_gen1(pdev) || pdev_is_gen3(pdev))
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xeon_deinit_dev(ndev);
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err_init_dev:
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intel_ntb_deinit_pci(ndev);
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@ -1921,7 +1918,7 @@ static void intel_ntb_pci_remove(struct pci_dev *pdev)
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ntb_unregister_device(&ndev->ntb);
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ndev_deinit_debugfs(ndev);
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if (pdev_is_xeon(pdev) || pdev_is_skx_xeon(pdev))
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if (pdev_is_gen1(pdev) || pdev_is_gen3(pdev))
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xeon_deinit_dev(ndev);
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intel_ntb_deinit_pci(ndev);
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kfree(ndev);
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@ -40,10 +40,8 @@
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* Intel PCIe NTB Linux driver
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* Intel PCIe GEN3 NTB Linux driver
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*
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* Contact Information:
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* Jon Mason <jon.mason@intel.com>
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*/
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#include <linux/debugfs.h>
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@ -60,37 +58,39 @@
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#include "ntb_hw_gen1.h"
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#include "ntb_hw_gen3.h"
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static const struct intel_ntb_reg skx_reg = {
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.poll_link = skx_poll_link,
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static int gen3_poll_link(struct intel_ntb_dev *ndev);
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static const struct intel_ntb_reg gen3_reg = {
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.poll_link = gen3_poll_link,
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.link_is_up = xeon_link_is_up,
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.db_ioread = skx_db_ioread,
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.db_iowrite = skx_db_iowrite,
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.db_ioread = gen3_db_ioread,
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.db_iowrite = gen3_db_iowrite,
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.db_size = sizeof(u32),
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.ntb_ctl = SKX_NTBCNTL_OFFSET,
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.ntb_ctl = GEN3_NTBCNTL_OFFSET,
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.mw_bar = {2, 4},
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};
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static const struct intel_ntb_alt_reg skx_pri_reg = {
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.db_bell = SKX_EM_DOORBELL_OFFSET,
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.db_clear = SKX_IM_INT_STATUS_OFFSET,
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.db_mask = SKX_IM_INT_DISABLE_OFFSET,
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.spad = SKX_IM_SPAD_OFFSET,
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static const struct intel_ntb_alt_reg gen3_pri_reg = {
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.db_bell = GEN3_EM_DOORBELL_OFFSET,
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.db_clear = GEN3_IM_INT_STATUS_OFFSET,
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.db_mask = GEN3_IM_INT_DISABLE_OFFSET,
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.spad = GEN3_IM_SPAD_OFFSET,
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};
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static const struct intel_ntb_alt_reg skx_b2b_reg = {
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.db_bell = SKX_IM_DOORBELL_OFFSET,
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.db_clear = SKX_EM_INT_STATUS_OFFSET,
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.db_mask = SKX_EM_INT_DISABLE_OFFSET,
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.spad = SKX_B2B_SPAD_OFFSET,
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static const struct intel_ntb_alt_reg gen3_b2b_reg = {
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.db_bell = GEN3_IM_DOORBELL_OFFSET,
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.db_clear = GEN3_EM_INT_STATUS_OFFSET,
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.db_mask = GEN3_EM_INT_DISABLE_OFFSET,
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.spad = GEN3_B2B_SPAD_OFFSET,
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};
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static const struct intel_ntb_xlat_reg skx_sec_xlat = {
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/* .bar0_base = SKX_EMBAR0_OFFSET, */
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.bar2_limit = SKX_IMBAR1XLMT_OFFSET,
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.bar2_xlat = SKX_IMBAR1XBASE_OFFSET,
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static const struct intel_ntb_xlat_reg gen3_sec_xlat = {
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/* .bar0_base = GEN3_EMBAR0_OFFSET, */
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.bar2_limit = GEN3_IMBAR1XLMT_OFFSET,
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.bar2_xlat = GEN3_IMBAR1XBASE_OFFSET,
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};
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int skx_poll_link(struct intel_ntb_dev *ndev)
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static int gen3_poll_link(struct intel_ntb_dev *ndev)
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{
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u16 reg_val;
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int rc;
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@ -100,7 +100,7 @@ int skx_poll_link(struct intel_ntb_dev *ndev)
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ndev->self_reg->db_clear);
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rc = pci_read_config_word(ndev->ntb.pdev,
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SKX_LINK_STATUS_OFFSET, ®_val);
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GEN3_LINK_STATUS_OFFSET, ®_val);
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if (rc)
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return 0;
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@ -112,7 +112,7 @@ int skx_poll_link(struct intel_ntb_dev *ndev)
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return 1;
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}
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static int skx_init_isr(struct intel_ntb_dev *ndev)
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static int gen3_init_isr(struct intel_ntb_dev *ndev)
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{
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int i;
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@ -123,23 +123,23 @@ static int skx_init_isr(struct intel_ntb_dev *ndev)
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* The vectors at reset is 1-32,0. We need to reprogram to 0-32.
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*/
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for (i = 0; i < SKX_DB_MSIX_VECTOR_COUNT; i++)
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iowrite8(i, ndev->self_mmio + SKX_INTVEC_OFFSET + i);
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for (i = 0; i < GEN3_DB_MSIX_VECTOR_COUNT; i++)
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iowrite8(i, ndev->self_mmio + GEN3_INTVEC_OFFSET + i);
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/* move link status down one as workaround */
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if (ndev->hwerr_flags & NTB_HWERR_MSIX_VECTOR32_BAD) {
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iowrite8(SKX_DB_MSIX_VECTOR_COUNT - 2,
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ndev->self_mmio + SKX_INTVEC_OFFSET +
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(SKX_DB_MSIX_VECTOR_COUNT - 1));
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iowrite8(GEN3_DB_MSIX_VECTOR_COUNT - 2,
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ndev->self_mmio + GEN3_INTVEC_OFFSET +
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(GEN3_DB_MSIX_VECTOR_COUNT - 1));
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}
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return ndev_init_isr(ndev, SKX_DB_MSIX_VECTOR_COUNT,
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SKX_DB_MSIX_VECTOR_COUNT,
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SKX_DB_MSIX_VECTOR_SHIFT,
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SKX_DB_TOTAL_SHIFT);
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return ndev_init_isr(ndev, GEN3_DB_MSIX_VECTOR_COUNT,
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GEN3_DB_MSIX_VECTOR_COUNT,
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GEN3_DB_MSIX_VECTOR_SHIFT,
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GEN3_DB_TOTAL_SHIFT);
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}
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static int skx_setup_b2b_mw(struct intel_ntb_dev *ndev,
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static int gen3_setup_b2b_mw(struct intel_ntb_dev *ndev,
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const struct intel_b2b_addr *addr,
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const struct intel_b2b_addr *peer_addr)
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{
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@ -152,33 +152,33 @@ static int skx_setup_b2b_mw(struct intel_ntb_dev *ndev,
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/* setup incoming bar limits == base addrs (zero length windows) */
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bar_addr = addr->bar2_addr64;
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iowrite64(bar_addr, mmio + SKX_IMBAR1XLMT_OFFSET);
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bar_addr = ioread64(mmio + SKX_IMBAR1XLMT_OFFSET);
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iowrite64(bar_addr, mmio + GEN3_IMBAR1XLMT_OFFSET);
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bar_addr = ioread64(mmio + GEN3_IMBAR1XLMT_OFFSET);
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dev_dbg(&pdev->dev, "IMBAR1XLMT %#018llx\n", bar_addr);
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bar_addr = addr->bar4_addr64;
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iowrite64(bar_addr, mmio + SKX_IMBAR2XLMT_OFFSET);
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bar_addr = ioread64(mmio + SKX_IMBAR2XLMT_OFFSET);
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iowrite64(bar_addr, mmio + GEN3_IMBAR2XLMT_OFFSET);
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bar_addr = ioread64(mmio + GEN3_IMBAR2XLMT_OFFSET);
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dev_dbg(&pdev->dev, "IMBAR2XLMT %#018llx\n", bar_addr);
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/* zero incoming translation addrs */
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iowrite64(0, mmio + SKX_IMBAR1XBASE_OFFSET);
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iowrite64(0, mmio + SKX_IMBAR2XBASE_OFFSET);
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iowrite64(0, mmio + GEN3_IMBAR1XBASE_OFFSET);
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iowrite64(0, mmio + GEN3_IMBAR2XBASE_OFFSET);
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ndev->peer_mmio = ndev->self_mmio;
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return 0;
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}
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static int skx_init_ntb(struct intel_ntb_dev *ndev)
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static int gen3_init_ntb(struct intel_ntb_dev *ndev)
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{
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int rc;
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ndev->mw_count = XEON_MW_COUNT;
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ndev->spad_count = SKX_SPAD_COUNT;
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ndev->db_count = SKX_DB_COUNT;
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ndev->db_link_mask = SKX_DB_LINK_BIT;
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ndev->spad_count = GEN3_SPAD_COUNT;
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ndev->db_count = GEN3_DB_COUNT;
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ndev->db_link_mask = GEN3_DB_LINK_BIT;
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/* DB fixup for using 31 right now */
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if (ndev->hwerr_flags & NTB_HWERR_MSIX_VECTOR32_BAD)
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@ -187,16 +187,16 @@ static int skx_init_ntb(struct intel_ntb_dev *ndev)
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switch (ndev->ntb.topo) {
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case NTB_TOPO_B2B_USD:
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case NTB_TOPO_B2B_DSD:
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ndev->self_reg = &skx_pri_reg;
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ndev->peer_reg = &skx_b2b_reg;
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ndev->xlat_reg = &skx_sec_xlat;
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ndev->self_reg = &gen3_pri_reg;
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ndev->peer_reg = &gen3_b2b_reg;
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ndev->xlat_reg = &gen3_sec_xlat;
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if (ndev->ntb.topo == NTB_TOPO_B2B_USD) {
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rc = skx_setup_b2b_mw(ndev,
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rc = gen3_setup_b2b_mw(ndev,
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&xeon_b2b_dsd_addr,
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&xeon_b2b_usd_addr);
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} else {
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rc = skx_setup_b2b_mw(ndev,
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rc = gen3_setup_b2b_mw(ndev,
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&xeon_b2b_usd_addr,
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&xeon_b2b_dsd_addr);
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}
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@ -206,7 +206,7 @@ static int skx_init_ntb(struct intel_ntb_dev *ndev)
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/* Enable Bus Master and Memory Space on the secondary side */
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iowrite16(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER,
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ndev->self_mmio + SKX_SPCICMD_OFFSET);
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ndev->self_mmio + GEN3_SPCICMD_OFFSET);
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break;
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@ -223,7 +223,7 @@ static int skx_init_ntb(struct intel_ntb_dev *ndev)
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return 0;
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}
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int skx_init_dev(struct intel_ntb_dev *ndev)
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int gen3_init_dev(struct intel_ntb_dev *ndev)
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{
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struct pci_dev *pdev;
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u8 ppd;
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@ -231,7 +231,7 @@ int skx_init_dev(struct intel_ntb_dev *ndev)
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pdev = ndev->ntb.pdev;
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ndev->reg = &skx_reg;
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ndev->reg = &gen3_reg;
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rc = pci_read_config_byte(pdev, XEON_PPD_OFFSET, &ppd);
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if (rc)
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@ -245,11 +245,11 @@ int skx_init_dev(struct intel_ntb_dev *ndev)
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ndev->hwerr_flags |= NTB_HWERR_MSIX_VECTOR32_BAD;
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rc = skx_init_ntb(ndev);
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rc = gen3_init_ntb(ndev);
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if (rc)
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return rc;
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return skx_init_isr(ndev);
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return gen3_init_isr(ndev);
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}
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ssize_t ndev_ntb3_debugfs_read(struct file *filp, char __user *ubuf,
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@ -328,19 +328,19 @@ ssize_t ndev_ntb3_debugfs_read(struct file *filp, char __user *ubuf,
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off += scnprintf(buf + off, buf_size - off,
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"\nNTB Incoming XLAT:\n");
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u.v64 = ioread64(mmio + SKX_IMBAR1XBASE_OFFSET);
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u.v64 = ioread64(mmio + GEN3_IMBAR1XBASE_OFFSET);
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off += scnprintf(buf + off, buf_size - off,
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"IMBAR1XBASE -\t\t%#018llx\n", u.v64);
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u.v64 = ioread64(mmio + SKX_IMBAR2XBASE_OFFSET);
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u.v64 = ioread64(mmio + GEN3_IMBAR2XBASE_OFFSET);
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off += scnprintf(buf + off, buf_size - off,
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"IMBAR2XBASE -\t\t%#018llx\n", u.v64);
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u.v64 = ioread64(mmio + SKX_IMBAR1XLMT_OFFSET);
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u.v64 = ioread64(mmio + GEN3_IMBAR1XLMT_OFFSET);
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off += scnprintf(buf + off, buf_size - off,
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"IMBAR1XLMT -\t\t\t%#018llx\n", u.v64);
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u.v64 = ioread64(mmio + SKX_IMBAR2XLMT_OFFSET);
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u.v64 = ioread64(mmio + GEN3_IMBAR2XLMT_OFFSET);
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off += scnprintf(buf + off, buf_size - off,
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"IMBAR2XLMT -\t\t\t%#018llx\n", u.v64);
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@ -348,34 +348,34 @@ ssize_t ndev_ntb3_debugfs_read(struct file *filp, char __user *ubuf,
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off += scnprintf(buf + off, buf_size - off,
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"\nNTB Outgoing B2B XLAT:\n");
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u.v64 = ioread64(mmio + SKX_EMBAR1XBASE_OFFSET);
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u.v64 = ioread64(mmio + GEN3_EMBAR1XBASE_OFFSET);
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off += scnprintf(buf + off, buf_size - off,
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"EMBAR1XBASE -\t\t%#018llx\n", u.v64);
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u.v64 = ioread64(mmio + SKX_EMBAR2XBASE_OFFSET);
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u.v64 = ioread64(mmio + GEN3_EMBAR2XBASE_OFFSET);
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off += scnprintf(buf + off, buf_size - off,
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"EMBAR2XBASE -\t\t%#018llx\n", u.v64);
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u.v64 = ioread64(mmio + SKX_EMBAR1XLMT_OFFSET);
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u.v64 = ioread64(mmio + GEN3_EMBAR1XLMT_OFFSET);
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off += scnprintf(buf + off, buf_size - off,
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"EMBAR1XLMT -\t\t%#018llx\n", u.v64);
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u.v64 = ioread64(mmio + SKX_EMBAR2XLMT_OFFSET);
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u.v64 = ioread64(mmio + GEN3_EMBAR2XLMT_OFFSET);
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off += scnprintf(buf + off, buf_size - off,
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"EMBAR2XLMT -\t\t%#018llx\n", u.v64);
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off += scnprintf(buf + off, buf_size - off,
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"\nNTB Secondary BAR:\n");
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u.v64 = ioread64(mmio + SKX_EMBAR0_OFFSET);
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u.v64 = ioread64(mmio + GEN3_EMBAR0_OFFSET);
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off += scnprintf(buf + off, buf_size - off,
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"EMBAR0 -\t\t%#018llx\n", u.v64);
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u.v64 = ioread64(mmio + SKX_EMBAR1_OFFSET);
|
||||
u.v64 = ioread64(mmio + GEN3_EMBAR1_OFFSET);
|
||||
off += scnprintf(buf + off, buf_size - off,
|
||||
"EMBAR1 -\t\t%#018llx\n", u.v64);
|
||||
|
||||
u.v64 = ioread64(mmio + SKX_EMBAR2_OFFSET);
|
||||
u.v64 = ioread64(mmio + GEN3_EMBAR2_OFFSET);
|
||||
off += scnprintf(buf + off, buf_size - off,
|
||||
"EMBAR2 -\t\t%#018llx\n", u.v64);
|
||||
}
|
||||
|
|
@ -383,7 +383,7 @@ ssize_t ndev_ntb3_debugfs_read(struct file *filp, char __user *ubuf,
|
|||
off += scnprintf(buf + off, buf_size - off,
|
||||
"\nNTB Statistics:\n");
|
||||
|
||||
u.v16 = ioread16(mmio + SKX_USMEMMISS_OFFSET);
|
||||
u.v16 = ioread16(mmio + GEN3_USMEMMISS_OFFSET);
|
||||
off += scnprintf(buf + off, buf_size - off,
|
||||
"Upstream Memory Miss -\t%u\n", u.v16);
|
||||
|
||||
|
|
@ -391,22 +391,22 @@ ssize_t ndev_ntb3_debugfs_read(struct file *filp, char __user *ubuf,
|
|||
"\nNTB Hardware Errors:\n");
|
||||
|
||||
if (!pci_read_config_word(ndev->ntb.pdev,
|
||||
SKX_DEVSTS_OFFSET, &u.v16))
|
||||
GEN3_DEVSTS_OFFSET, &u.v16))
|
||||
off += scnprintf(buf + off, buf_size - off,
|
||||
"DEVSTS -\t\t%#06x\n", u.v16);
|
||||
|
||||
if (!pci_read_config_word(ndev->ntb.pdev,
|
||||
SKX_LINK_STATUS_OFFSET, &u.v16))
|
||||
GEN3_LINK_STATUS_OFFSET, &u.v16))
|
||||
off += scnprintf(buf + off, buf_size - off,
|
||||
"LNKSTS -\t\t%#06x\n", u.v16);
|
||||
|
||||
if (!pci_read_config_dword(ndev->ntb.pdev,
|
||||
SKX_UNCERRSTS_OFFSET, &u.v32))
|
||||
GEN3_UNCERRSTS_OFFSET, &u.v32))
|
||||
off += scnprintf(buf + off, buf_size - off,
|
||||
"UNCERRSTS -\t\t%#06x\n", u.v32);
|
||||
|
||||
if (!pci_read_config_dword(ndev->ntb.pdev,
|
||||
SKX_CORERRSTS_OFFSET, &u.v32))
|
||||
GEN3_CORERRSTS_OFFSET, &u.v32))
|
||||
off += scnprintf(buf + off, buf_size - off,
|
||||
"CORERRSTS -\t\t%#06x\n", u.v32);
|
||||
|
||||
|
|
@ -510,7 +510,7 @@ static int intel_ntb3_mw_set_trans(struct ntb_dev *ntb, int pidx, int idx,
|
|||
|
||||
/* setup the EP */
|
||||
limit_reg = ndev->xlat_reg->bar2_limit + (idx * 0x10) + 0x4000;
|
||||
base = ioread64(mmio + SKX_EMBAR1_OFFSET + (8 * idx));
|
||||
base = ioread64(mmio + GEN3_EMBAR1_OFFSET + (8 * idx));
|
||||
base &= ~0xf;
|
||||
|
||||
if (limit_reg && size != mw_size)
|
||||
|
|
|
|||
|
|
@ -47,64 +47,63 @@
|
|||
#include "ntb_hw_intel.h"
|
||||
|
||||
/* Intel Skylake Xeon hardware */
|
||||
#define SKX_IMBAR1SZ_OFFSET 0x00d0
|
||||
#define SKX_IMBAR2SZ_OFFSET 0x00d1
|
||||
#define SKX_EMBAR1SZ_OFFSET 0x00d2
|
||||
#define SKX_EMBAR2SZ_OFFSET 0x00d3
|
||||
#define SKX_DEVCTRL_OFFSET 0x0098
|
||||
#define SKX_DEVSTS_OFFSET 0x009a
|
||||
#define SKX_UNCERRSTS_OFFSET 0x014c
|
||||
#define SKX_CORERRSTS_OFFSET 0x0158
|
||||
#define SKX_LINK_STATUS_OFFSET 0x01a2
|
||||
#define GEN3_IMBAR1SZ_OFFSET 0x00d0
|
||||
#define GEN3_IMBAR2SZ_OFFSET 0x00d1
|
||||
#define GEN3_EMBAR1SZ_OFFSET 0x00d2
|
||||
#define GEN3_EMBAR2SZ_OFFSET 0x00d3
|
||||
#define GEN3_DEVCTRL_OFFSET 0x0098
|
||||
#define GEN3_DEVSTS_OFFSET 0x009a
|
||||
#define GEN3_UNCERRSTS_OFFSET 0x014c
|
||||
#define GEN3_CORERRSTS_OFFSET 0x0158
|
||||
#define GEN3_LINK_STATUS_OFFSET 0x01a2
|
||||
|
||||
#define SKX_NTBCNTL_OFFSET 0x0000
|
||||
#define SKX_IMBAR1XBASE_OFFSET 0x0010 /* SBAR2XLAT */
|
||||
#define SKX_IMBAR1XLMT_OFFSET 0x0018 /* SBAR2LMT */
|
||||
#define SKX_IMBAR2XBASE_OFFSET 0x0020 /* SBAR4XLAT */
|
||||
#define SKX_IMBAR2XLMT_OFFSET 0x0028 /* SBAR4LMT */
|
||||
#define SKX_IM_INT_STATUS_OFFSET 0x0040
|
||||
#define SKX_IM_INT_DISABLE_OFFSET 0x0048
|
||||
#define SKX_IM_SPAD_OFFSET 0x0080 /* SPAD */
|
||||
#define SKX_USMEMMISS_OFFSET 0x0070
|
||||
#define SKX_INTVEC_OFFSET 0x00d0
|
||||
#define SKX_IM_DOORBELL_OFFSET 0x0100 /* SDOORBELL0 */
|
||||
#define SKX_B2B_SPAD_OFFSET 0x0180 /* B2B SPAD */
|
||||
#define SKX_EMBAR0XBASE_OFFSET 0x4008 /* B2B_XLAT */
|
||||
#define SKX_EMBAR1XBASE_OFFSET 0x4010 /* PBAR2XLAT */
|
||||
#define SKX_EMBAR1XLMT_OFFSET 0x4018 /* PBAR2LMT */
|
||||
#define SKX_EMBAR2XBASE_OFFSET 0x4020 /* PBAR4XLAT */
|
||||
#define SKX_EMBAR2XLMT_OFFSET 0x4028 /* PBAR4LMT */
|
||||
#define SKX_EM_INT_STATUS_OFFSET 0x4040
|
||||
#define SKX_EM_INT_DISABLE_OFFSET 0x4048
|
||||
#define SKX_EM_SPAD_OFFSET 0x4080 /* remote SPAD */
|
||||
#define SKX_EM_DOORBELL_OFFSET 0x4100 /* PDOORBELL0 */
|
||||
#define SKX_SPCICMD_OFFSET 0x4504 /* SPCICMD */
|
||||
#define SKX_EMBAR0_OFFSET 0x4510 /* SBAR0BASE */
|
||||
#define SKX_EMBAR1_OFFSET 0x4518 /* SBAR23BASE */
|
||||
#define SKX_EMBAR2_OFFSET 0x4520 /* SBAR45BASE */
|
||||
#define GEN3_NTBCNTL_OFFSET 0x0000
|
||||
#define GEN3_IMBAR1XBASE_OFFSET 0x0010 /* SBAR2XLAT */
|
||||
#define GEN3_IMBAR1XLMT_OFFSET 0x0018 /* SBAR2LMT */
|
||||
#define GEN3_IMBAR2XBASE_OFFSET 0x0020 /* SBAR4XLAT */
|
||||
#define GEN3_IMBAR2XLMT_OFFSET 0x0028 /* SBAR4LMT */
|
||||
#define GEN3_IM_INT_STATUS_OFFSET 0x0040
|
||||
#define GEN3_IM_INT_DISABLE_OFFSET 0x0048
|
||||
#define GEN3_IM_SPAD_OFFSET 0x0080 /* SPAD */
|
||||
#define GEN3_USMEMMISS_OFFSET 0x0070
|
||||
#define GEN3_INTVEC_OFFSET 0x00d0
|
||||
#define GEN3_IM_DOORBELL_OFFSET 0x0100 /* SDOORBELL0 */
|
||||
#define GEN3_B2B_SPAD_OFFSET 0x0180 /* B2B SPAD */
|
||||
#define GEN3_EMBAR0XBASE_OFFSET 0x4008 /* B2B_XLAT */
|
||||
#define GEN3_EMBAR1XBASE_OFFSET 0x4010 /* PBAR2XLAT */
|
||||
#define GEN3_EMBAR1XLMT_OFFSET 0x4018 /* PBAR2LMT */
|
||||
#define GEN3_EMBAR2XBASE_OFFSET 0x4020 /* PBAR4XLAT */
|
||||
#define GEN3_EMBAR2XLMT_OFFSET 0x4028 /* PBAR4LMT */
|
||||
#define GEN3_EM_INT_STATUS_OFFSET 0x4040
|
||||
#define GEN3_EM_INT_DISABLE_OFFSET 0x4048
|
||||
#define GEN3_EM_SPAD_OFFSET 0x4080 /* remote SPAD */
|
||||
#define GEN3_EM_DOORBELL_OFFSET 0x4100 /* PDOORBELL0 */
|
||||
#define GEN3_SPCICMD_OFFSET 0x4504 /* SPCICMD */
|
||||
#define GEN3_EMBAR0_OFFSET 0x4510 /* SBAR0BASE */
|
||||
#define GEN3_EMBAR1_OFFSET 0x4518 /* SBAR23BASE */
|
||||
#define GEN3_EMBAR2_OFFSET 0x4520 /* SBAR45BASE */
|
||||
|
||||
#define SKX_DB_COUNT 32
|
||||
#define SKX_DB_LINK 32
|
||||
#define SKX_DB_LINK_BIT BIT_ULL(SKX_DB_LINK)
|
||||
#define SKX_DB_MSIX_VECTOR_COUNT 33
|
||||
#define SKX_DB_MSIX_VECTOR_SHIFT 1
|
||||
#define SKX_DB_TOTAL_SHIFT 33
|
||||
#define SKX_SPAD_COUNT 16
|
||||
#define GEN3_DB_COUNT 32
|
||||
#define GEN3_DB_LINK 32
|
||||
#define GEN3_DB_LINK_BIT BIT_ULL(GEN3_DB_LINK)
|
||||
#define GEN3_DB_MSIX_VECTOR_COUNT 33
|
||||
#define GEN3_DB_MSIX_VECTOR_SHIFT 1
|
||||
#define GEN3_DB_TOTAL_SHIFT 33
|
||||
#define GEN3_SPAD_COUNT 16
|
||||
|
||||
static inline u64 skx_db_ioread(void __iomem *mmio)
|
||||
static inline u64 gen3_db_ioread(void __iomem *mmio)
|
||||
{
|
||||
return ioread64(mmio);
|
||||
}
|
||||
|
||||
static inline void skx_db_iowrite(u64 bits, void __iomem *mmio)
|
||||
static inline void gen3_db_iowrite(u64 bits, void __iomem *mmio)
|
||||
{
|
||||
iowrite64(bits, mmio);
|
||||
}
|
||||
|
||||
ssize_t ndev_ntb3_debugfs_read(struct file *filp, char __user *ubuf,
|
||||
size_t count, loff_t *offp);
|
||||
int skx_init_dev(struct intel_ntb_dev *ndev);
|
||||
int skx_poll_link(struct intel_ntb_dev *ndev);
|
||||
int gen3_init_dev(struct intel_ntb_dev *ndev);
|
||||
|
||||
extern const struct ntb_dev_ops intel_ntb3_ops;
|
||||
|
||||
|
|
|
|||
|
|
@ -187,7 +187,7 @@ struct intel_ntb_dev {
|
|||
#define hb_ndev(__work) container_of(__work, struct intel_ntb_dev, \
|
||||
hb_timer.work)
|
||||
|
||||
static inline int pdev_is_xeon(struct pci_dev *pdev)
|
||||
static inline int pdev_is_gen1(struct pci_dev *pdev)
|
||||
{
|
||||
switch (pdev->device) {
|
||||
case PCI_DEVICE_ID_INTEL_NTB_SS_JSF:
|
||||
|
|
@ -210,7 +210,7 @@ static inline int pdev_is_xeon(struct pci_dev *pdev)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static inline int pdev_is_skx_xeon(struct pci_dev *pdev)
|
||||
static inline int pdev_is_gen3(struct pci_dev *pdev)
|
||||
{
|
||||
if (pdev->device == PCI_DEVICE_ID_INTEL_NTB_B2B_SKX)
|
||||
return 1;
|
||||
|
|
|
|||
Loading…
Reference in New Issue