MIPS: ptrace: Remove FP support when CONFIG_MIPS_FP_SUPPORT=n
When CONFIG_MIPS_FP_SUPPORT=n we don't support floating point, so remove the related ptrace support. Besides removing code which should not be needed, this prepares us for the removal of FPU state in struct task_struct which this code requires. Signed-off-by: Paul Burton <paul.burton@mips.com> Patchwork: https://patchwork.linux-mips.org/patch/21008/ Cc: linux-mips@linux-mips.orghifive-unleashed-5.1
Paul Burton
parent
85164fd8b0
commit
6c79759eca
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@ -61,21 +61,6 @@ void ptrace_disable(struct task_struct *child)
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clear_tsk_thread_flag(child, TIF_LOAD_WATCH);
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}
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/*
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* Poke at FCSR according to its mask. Set the Cause bits even
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* if a corresponding Enable bit is set. This will be noticed at
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* the time the thread is switched to and SIGFPE thrown accordingly.
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*/
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static void ptrace_setfcr31(struct task_struct *child, u32 value)
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{
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u32 fcr31;
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u32 mask;
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fcr31 = child->thread.fpu.fcr31;
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mask = boot_cpu_data.fpu_msk31;
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child->thread.fpu.fcr31 = (value & ~mask) | (fcr31 & mask);
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}
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/*
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* Read a general register set. We always use the 64-bit format, even
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* for 32-bit kernels and for 32-bit processes on a 64-bit kernel.
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@ -132,55 +117,6 @@ int ptrace_setregs(struct task_struct *child, struct user_pt_regs __user *data)
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return 0;
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}
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int ptrace_getfpregs(struct task_struct *child, __u32 __user *data)
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{
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int i;
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if (!access_ok(VERIFY_WRITE, data, 33 * 8))
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return -EIO;
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if (tsk_used_math(child)) {
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union fpureg *fregs = get_fpu_regs(child);
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for (i = 0; i < 32; i++)
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__put_user(get_fpr64(&fregs[i], 0),
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i + (__u64 __user *)data);
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} else {
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for (i = 0; i < 32; i++)
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__put_user((__u64) -1, i + (__u64 __user *) data);
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}
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__put_user(child->thread.fpu.fcr31, data + 64);
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__put_user(boot_cpu_data.fpu_id, data + 65);
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return 0;
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}
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int ptrace_setfpregs(struct task_struct *child, __u32 __user *data)
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{
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union fpureg *fregs;
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u64 fpr_val;
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u32 value;
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int i;
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if (!access_ok(VERIFY_READ, data, 33 * 8))
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return -EIO;
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init_fp_ctx(child);
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fregs = get_fpu_regs(child);
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for (i = 0; i < 32; i++) {
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__get_user(fpr_val, i + (__u64 __user *)data);
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set_fpr64(&fregs[i], 0, fpr_val);
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}
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__get_user(value, data + 64);
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ptrace_setfcr31(child, value);
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/* FIR may not be written. */
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return 0;
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}
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int ptrace_get_watch_regs(struct task_struct *child,
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struct pt_watch_regs __user *addr)
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{
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@ -401,6 +337,73 @@ static int gpr64_set(struct task_struct *target,
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#endif /* CONFIG_64BIT */
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#ifdef CONFIG_MIPS_FP_SUPPORT
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/*
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* Poke at FCSR according to its mask. Set the Cause bits even
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* if a corresponding Enable bit is set. This will be noticed at
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* the time the thread is switched to and SIGFPE thrown accordingly.
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*/
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static void ptrace_setfcr31(struct task_struct *child, u32 value)
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{
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u32 fcr31;
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u32 mask;
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fcr31 = child->thread.fpu.fcr31;
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mask = boot_cpu_data.fpu_msk31;
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child->thread.fpu.fcr31 = (value & ~mask) | (fcr31 & mask);
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}
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int ptrace_getfpregs(struct task_struct *child, __u32 __user *data)
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{
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int i;
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if (!access_ok(VERIFY_WRITE, data, 33 * 8))
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return -EIO;
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if (tsk_used_math(child)) {
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union fpureg *fregs = get_fpu_regs(child);
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for (i = 0; i < 32; i++)
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__put_user(get_fpr64(&fregs[i], 0),
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i + (__u64 __user *)data);
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} else {
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for (i = 0; i < 32; i++)
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__put_user((__u64) -1, i + (__u64 __user *) data);
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}
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__put_user(child->thread.fpu.fcr31, data + 64);
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__put_user(boot_cpu_data.fpu_id, data + 65);
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return 0;
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}
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int ptrace_setfpregs(struct task_struct *child, __u32 __user *data)
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{
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union fpureg *fregs;
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u64 fpr_val;
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u32 value;
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int i;
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if (!access_ok(VERIFY_READ, data, 33 * 8))
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return -EIO;
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init_fp_ctx(child);
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fregs = get_fpu_regs(child);
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for (i = 0; i < 32; i++) {
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__get_user(fpr_val, i + (__u64 __user *)data);
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set_fpr64(&fregs[i], 0, fpr_val);
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}
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__get_user(value, data + 64);
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ptrace_setfcr31(child, value);
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/* FIR may not be written. */
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return 0;
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}
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/*
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* Copy the floating-point context to the supplied NT_PRFPREG buffer,
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* !CONFIG_CPU_HAS_MSA variant. FP context's general register slots
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@ -571,6 +574,54 @@ static int fpr_set(struct task_struct *target,
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return err;
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}
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/* Copy the FP mode setting to the supplied NT_MIPS_FP_MODE buffer. */
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static int fp_mode_get(struct task_struct *target,
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const struct user_regset *regset,
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unsigned int pos, unsigned int count,
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void *kbuf, void __user *ubuf)
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{
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int fp_mode;
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fp_mode = mips_get_process_fp_mode(target);
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return user_regset_copyout(&pos, &count, &kbuf, &ubuf, &fp_mode, 0,
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sizeof(fp_mode));
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}
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/*
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* Copy the supplied NT_MIPS_FP_MODE buffer to the FP mode setting.
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*
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* We optimize for the case where `count % sizeof(int) == 0', which
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* is supposed to have been guaranteed by the kernel before calling
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* us, e.g. in `ptrace_regset'. We enforce that requirement, so
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* that we can safely avoid preinitializing temporaries for partial
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* mode writes.
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*/
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static int fp_mode_set(struct task_struct *target,
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const struct user_regset *regset,
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unsigned int pos, unsigned int count,
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const void *kbuf, const void __user *ubuf)
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{
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int fp_mode;
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int err;
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BUG_ON(count % sizeof(int));
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if (pos + count > sizeof(fp_mode))
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return -EIO;
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err = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &fp_mode, 0,
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sizeof(fp_mode));
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if (err)
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return err;
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if (count > 0)
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err = mips_set_process_fp_mode(target, fp_mode);
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return err;
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}
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#endif /* CONFIG_MIPS_FP_SUPPORT */
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#if defined(CONFIG_32BIT) || defined(CONFIG_MIPS32_O32)
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/*
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@ -740,57 +791,13 @@ static int dsp_active(struct task_struct *target,
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return cpu_has_dsp ? NUM_DSP_REGS + 1 : -ENODEV;
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}
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/* Copy the FP mode setting to the supplied NT_MIPS_FP_MODE buffer. */
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static int fp_mode_get(struct task_struct *target,
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const struct user_regset *regset,
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unsigned int pos, unsigned int count,
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void *kbuf, void __user *ubuf)
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{
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int fp_mode;
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fp_mode = mips_get_process_fp_mode(target);
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return user_regset_copyout(&pos, &count, &kbuf, &ubuf, &fp_mode, 0,
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sizeof(fp_mode));
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}
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/*
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* Copy the supplied NT_MIPS_FP_MODE buffer to the FP mode setting.
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*
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* We optimize for the case where `count % sizeof(int) == 0', which
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* is supposed to have been guaranteed by the kernel before calling
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* us, e.g. in `ptrace_regset'. We enforce that requirement, so
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* that we can safely avoid preinitializing temporaries for partial
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* mode writes.
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*/
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static int fp_mode_set(struct task_struct *target,
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const struct user_regset *regset,
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unsigned int pos, unsigned int count,
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const void *kbuf, const void __user *ubuf)
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{
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int fp_mode;
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int err;
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BUG_ON(count % sizeof(int));
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if (pos + count > sizeof(fp_mode))
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return -EIO;
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err = user_regset_copyin(&pos, &count, &kbuf, &ubuf, &fp_mode, 0,
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sizeof(fp_mode));
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if (err)
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return err;
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if (count > 0)
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err = mips_set_process_fp_mode(target, fp_mode);
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return err;
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}
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enum mips_regset {
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REGSET_GPR,
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REGSET_FPR,
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REGSET_DSP,
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#ifdef CONFIG_MIPS_FP_SUPPORT
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REGSET_FPR,
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REGSET_FP_MODE,
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#endif
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};
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struct pt_regs_offset {
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@ -888,14 +895,6 @@ static const struct user_regset mips_regsets[] = {
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.get = gpr32_get,
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.set = gpr32_set,
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},
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[REGSET_FPR] = {
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.core_note_type = NT_PRFPREG,
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.n = ELF_NFPREG,
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.size = sizeof(elf_fpreg_t),
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.align = sizeof(elf_fpreg_t),
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.get = fpr_get,
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.set = fpr_set,
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},
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[REGSET_DSP] = {
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.core_note_type = NT_MIPS_DSP,
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.n = NUM_DSP_REGS + 1,
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@ -905,6 +904,15 @@ static const struct user_regset mips_regsets[] = {
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.set = dsp32_set,
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.active = dsp_active,
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},
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#ifdef CONFIG_MIPS_FP_SUPPORT
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[REGSET_FPR] = {
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.core_note_type = NT_PRFPREG,
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.n = ELF_NFPREG,
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.size = sizeof(elf_fpreg_t),
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.align = sizeof(elf_fpreg_t),
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.get = fpr_get,
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.set = fpr_set,
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},
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[REGSET_FP_MODE] = {
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.core_note_type = NT_MIPS_FP_MODE,
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.n = 1,
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@ -913,6 +921,7 @@ static const struct user_regset mips_regsets[] = {
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.get = fp_mode_get,
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.set = fp_mode_set,
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},
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#endif
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};
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static const struct user_regset_view user_mips_view = {
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@ -936,14 +945,6 @@ static const struct user_regset mips64_regsets[] = {
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.get = gpr64_get,
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.set = gpr64_set,
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},
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[REGSET_FPR] = {
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.core_note_type = NT_PRFPREG,
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.n = ELF_NFPREG,
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.size = sizeof(elf_fpreg_t),
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.align = sizeof(elf_fpreg_t),
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.get = fpr_get,
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.set = fpr_set,
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},
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[REGSET_DSP] = {
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.core_note_type = NT_MIPS_DSP,
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.n = NUM_DSP_REGS + 1,
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@ -953,6 +954,7 @@ static const struct user_regset mips64_regsets[] = {
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.set = dsp64_set,
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.active = dsp_active,
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},
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#ifdef CONFIG_MIPS_FP_SUPPORT
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[REGSET_FP_MODE] = {
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.core_note_type = NT_MIPS_FP_MODE,
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.n = 1,
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@ -961,6 +963,15 @@ static const struct user_regset mips64_regsets[] = {
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.get = fp_mode_get,
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.set = fp_mode_set,
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},
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[REGSET_FPR] = {
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.core_note_type = NT_PRFPREG,
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.n = ELF_NFPREG,
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.size = sizeof(elf_fpreg_t),
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.align = sizeof(elf_fpreg_t),
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.get = fpr_get,
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.set = fpr_set,
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},
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#endif
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};
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static const struct user_regset_view user_mips64_view = {
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@ -1021,7 +1032,6 @@ long arch_ptrace(struct task_struct *child, long request,
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/* Read the word at location addr in the USER area. */
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case PTRACE_PEEKUSR: {
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struct pt_regs *regs;
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union fpureg *fregs;
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unsigned long tmp = 0;
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regs = task_pt_regs(child);
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@ -1031,7 +1041,10 @@ long arch_ptrace(struct task_struct *child, long request,
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case 0 ... 31:
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tmp = regs->regs[addr];
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break;
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case FPR_BASE ... FPR_BASE + 31:
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#ifdef CONFIG_MIPS_FP_SUPPORT
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case FPR_BASE ... FPR_BASE + 31: {
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union fpureg *fregs;
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if (!tsk_used_math(child)) {
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/* FP not yet used */
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tmp = -1;
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@ -1053,6 +1066,15 @@ long arch_ptrace(struct task_struct *child, long request,
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#endif
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tmp = get_fpr64(&fregs[addr - FPR_BASE], 0);
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break;
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}
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case FPC_CSR:
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tmp = child->thread.fpu.fcr31;
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break;
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case FPC_EIR:
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/* implementation / version register */
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tmp = boot_cpu_data.fpu_id;
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break;
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#endif
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case PC:
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tmp = regs->cp0_epc;
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break;
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@ -1073,13 +1095,6 @@ long arch_ptrace(struct task_struct *child, long request,
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tmp = regs->acx;
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break;
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#endif
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case FPC_CSR:
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tmp = child->thread.fpu.fcr31;
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break;
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case FPC_EIR:
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/* implementation / version register */
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tmp = boot_cpu_data.fpu_id;
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break;
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case DSP_BASE ... DSP_BASE + 5: {
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dspreg_t *dregs;
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@ -1130,6 +1145,7 @@ long arch_ptrace(struct task_struct *child, long request,
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mips_syscall_is_indirect(child, regs))
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mips_syscall_update_nr(child, regs);
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break;
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#ifdef CONFIG_MIPS_FP_SUPPORT
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case FPR_BASE ... FPR_BASE + 31: {
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union fpureg *fregs = get_fpu_regs(child);
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@ -1149,6 +1165,11 @@ long arch_ptrace(struct task_struct *child, long request,
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set_fpr64(&fregs[addr - FPR_BASE], 0, data);
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break;
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}
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case FPC_CSR:
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init_fp_ctx(child);
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ptrace_setfcr31(child, data);
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break;
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#endif
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case PC:
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regs->cp0_epc = data;
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break;
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@ -1163,10 +1184,6 @@ long arch_ptrace(struct task_struct *child, long request,
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regs->acx = data;
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break;
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#endif
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case FPC_CSR:
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init_fp_ctx(child);
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ptrace_setfcr31(child, data);
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break;
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case DSP_BASE ... DSP_BASE + 5: {
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dspreg_t *dregs;
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@ -1202,6 +1219,7 @@ long arch_ptrace(struct task_struct *child, long request,
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ret = ptrace_setregs(child, datavp);
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break;
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#ifdef CONFIG_MIPS_FP_SUPPORT
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case PTRACE_GETFPREGS:
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ret = ptrace_getfpregs(child, datavp);
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break;
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@ -1209,7 +1227,7 @@ long arch_ptrace(struct task_struct *child, long request,
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case PTRACE_SETFPREGS:
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ret = ptrace_setfpregs(child, datavp);
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break;
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#endif
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case PTRACE_GET_THREAD_AREA:
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ret = put_user(task_thread_info(child)->tp_value, datalp);
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break;
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@ -82,7 +82,6 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
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/* Read the word at location addr in the USER area. */
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case PTRACE_PEEKUSR: {
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struct pt_regs *regs;
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union fpureg *fregs;
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unsigned int tmp;
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regs = task_pt_regs(child);
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@ -92,7 +91,10 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
|
|||
case 0 ... 31:
|
||||
tmp = regs->regs[addr];
|
||||
break;
|
||||
case FPR_BASE ... FPR_BASE + 31:
|
||||
#ifdef CONFIG_MIPS_FP_SUPPORT
|
||||
case FPR_BASE ... FPR_BASE + 31: {
|
||||
union fpureg *fregs;
|
||||
|
||||
if (!tsk_used_math(child)) {
|
||||
/* FP not yet used */
|
||||
tmp = -1;
|
||||
|
|
@ -111,6 +113,15 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
|
|||
}
|
||||
tmp = get_fpr64(&fregs[addr - FPR_BASE], 0);
|
||||
break;
|
||||
}
|
||||
case FPC_CSR:
|
||||
tmp = child->thread.fpu.fcr31;
|
||||
break;
|
||||
case FPC_EIR:
|
||||
/* implementation / version register */
|
||||
tmp = boot_cpu_data.fpu_id;
|
||||
break;
|
||||
#endif /* CONFIG_MIPS_FP_SUPPORT */
|
||||
case PC:
|
||||
tmp = regs->cp0_epc;
|
||||
break;
|
||||
|
|
@ -126,13 +137,6 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
|
|||
case MMLO:
|
||||
tmp = regs->lo;
|
||||
break;
|
||||
case FPC_CSR:
|
||||
tmp = child->thread.fpu.fcr31;
|
||||
break;
|
||||
case FPC_EIR:
|
||||
/* implementation / version register */
|
||||
tmp = boot_cpu_data.fpu_id;
|
||||
break;
|
||||
case DSP_BASE ... DSP_BASE + 5: {
|
||||
dspreg_t *dregs;
|
||||
|
||||
|
|
@ -203,6 +207,7 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
|
|||
mips_syscall_is_indirect(child, regs))
|
||||
mips_syscall_update_nr(child, regs);
|
||||
break;
|
||||
#ifdef CONFIG_MIPS_FP_SUPPORT
|
||||
case FPR_BASE ... FPR_BASE + 31: {
|
||||
union fpureg *fregs = get_fpu_regs(child);
|
||||
|
||||
|
|
@ -225,6 +230,10 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
|
|||
set_fpr64(&fregs[addr - FPR_BASE], 0, data);
|
||||
break;
|
||||
}
|
||||
case FPC_CSR:
|
||||
child->thread.fpu.fcr31 = data;
|
||||
break;
|
||||
#endif /* CONFIG_MIPS_FP_SUPPORT */
|
||||
case PC:
|
||||
regs->cp0_epc = data;
|
||||
break;
|
||||
|
|
@ -234,9 +243,6 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
|
|||
case MMLO:
|
||||
regs->lo = data;
|
||||
break;
|
||||
case FPC_CSR:
|
||||
child->thread.fpu.fcr31 = data;
|
||||
break;
|
||||
case DSP_BASE ... DSP_BASE + 5: {
|
||||
dspreg_t *dregs;
|
||||
|
||||
|
|
@ -274,6 +280,7 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
|
|||
(struct user_pt_regs __user *) (__u64) data);
|
||||
break;
|
||||
|
||||
#ifdef CONFIG_MIPS_FP_SUPPORT
|
||||
case PTRACE_GETFPREGS:
|
||||
ret = ptrace_getfpregs(child, (__u32 __user *) (__u64) data);
|
||||
break;
|
||||
|
|
@ -281,7 +288,7 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
|
|||
case PTRACE_SETFPREGS:
|
||||
ret = ptrace_setfpregs(child, (__u32 __user *) (__u64) data);
|
||||
break;
|
||||
|
||||
#endif
|
||||
case PTRACE_GET_THREAD_AREA:
|
||||
ret = put_user(task_thread_info(child)->tp_value,
|
||||
(unsigned int __user *) (unsigned long) data);
|
||||
|
|
|
|||
Loading…
Reference in New Issue