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ASoC: fsl_ssi: Don't try to round-up for PM divisor calculation 

According to i.MX6 Series Reference Manual, the formula to calculate
the sys clock is

sysclk rate = bclk rate * (div2 + 1) * (7 * psr + 1) * (pm + 1) * 2

Commit aafa85e71a ("ASoC: fsl_ssi: Add DAI master mode support for
SSI on i.MX series") added the divisor calculation which relies on
the clk_round_rate(). However, at that time, clk_round_rate() didn't
provide closest clock rates for some cases because it might not use
a correct rounding policy. So using the original formula (pm + 1) for
PM divisor was not able to give us a desired clock rate. And then we
used (pm + 2) to do the trick.

However, the clk-divider driver has been refined a lot since commit
b11d282dbe ("clk: divider: fix rate calculation for fractional rates")
Now using (pm + 2) trick would result an incorrect clock rate.

So this patch fixes the problem by removing the useless trick.

Reported-by: Stephane Cerveau <scerveau@voxtok.com>
Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
hifive-unleashed-5.1
Nicolin Chen 2015-03-04 21:05:04 -08:00 committed by Mark Brown
parent 90aff15b3e
commit 6c8ca30eec
1 changed files with 1 additions and 1 deletions
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2
sound/soc/fsl/fsl_ssi.c
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@ -603,7 +603,7 @@ static int fsl_ssi_set_bclk(struct snd_pcm_substream *substream,
factor = (div2 + 1) * (7 * psr + 1) * 2;
for (i = 0; i < 255; i++) {
tmprate = freq * factor * (i + 2);
tmprate = freq * factor * (i + 1);
if (baudclk_is_used)
clkrate = clk_get_rate(ssi_private->baudclk);