powerpc/pci: Add IP revision register define for Freescale PCIe controller
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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@ -16,6 +16,7 @@
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#define PCIE_LTSSM 0x0404 /* PCIE Link Training and Status */
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#define PCIE_LTSSM 0x0404 /* PCIE Link Training and Status */
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#define PCIE_LTSSM_L0 0x16 /* L0 state */
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#define PCIE_LTSSM_L0 0x16 /* L0 state */
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#define PCIE_IP_REV_2_2 0x02080202 /* PCIE IP block version Rev2.2 */
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#define PIWAR_EN 0x80000000 /* Enable */
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#define PIWAR_EN 0x80000000 /* Enable */
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#define PIWAR_PF 0x20000000 /* prefetch */
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#define PIWAR_PF 0x20000000 /* prefetch */
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#define PIWAR_TGI_LOCAL 0x00f00000 /* target - local memory */
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#define PIWAR_TGI_LOCAL 0x00f00000 /* target - local memory */
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@ -57,7 +58,9 @@ struct ccsr_pci {
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__be32 pex_pme_mes_disr; /* 0x.024 - PCIE PME and message disable register */
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__be32 pex_pme_mes_disr; /* 0x.024 - PCIE PME and message disable register */
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__be32 pex_pme_mes_ier; /* 0x.028 - PCIE PME and message interrupt enable register */
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__be32 pex_pme_mes_ier; /* 0x.028 - PCIE PME and message interrupt enable register */
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__be32 pex_pmcr; /* 0x.02c - PCIE power management command register */
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__be32 pex_pmcr; /* 0x.02c - PCIE power management command register */
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u8 res3[3024];
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u8 res3[3016];
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__be32 block_rev1; /* 0x.bf8 - PCIE Block Revision register 1 */
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__be32 block_rev2; /* 0x.bfc - PCIE Block Revision register 2 */
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/* PCI/PCI Express outbound window 0-4
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/* PCI/PCI Express outbound window 0-4
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* Window 0 is the default window and is the only window enabled upon reset.
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* Window 0 is the default window and is the only window enabled upon reset.
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