Blackfin arch: remove non-bf54x ifdef logic since this file is only compiled on bf54x parts
Signed-off-by: Mike Frysinger <vapier.adi@gmail.com> Signed-off-by: Bryan Wu <cooloney@kernel.org>
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@ -73,25 +73,19 @@ ENTRY(_start_dma_code)
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w[p0] = r0.l;
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ssync;
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#if defined(CONFIG_BF54x)
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/* enable self refresh via SRREQ */
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P2.H = hi(EBIU_RSTCTL);
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P2.L = lo(EBIU_RSTCTL);
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R0 = [P2];
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BITSET (R0, 3);
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#else
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P2.H = hi(EBIU_SDGCTL);
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P2.L = lo(EBIU_SDGCTL);
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R0 = [P2];
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BITSET (R0, 24);
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#endif
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[P2] = R0;
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SSYNC;
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#if defined(CONFIG_BF54x)
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/* wait for SRACK bit to be set */
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.LSRR_MODE:
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R0 = [P2];
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CC = BITTST(R0, 4);
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if !CC JUMP .LSRR_MODE;
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#endif
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r0 = CONFIG_VCO_MULT & 63; /* Load the VCO multiplier */
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r0 = r0 << 9; /* Shift it over, */
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@ -123,7 +117,7 @@ ENTRY(_start_dma_code)
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w[p0] = r0.l;
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ssync;
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#if defined(CONFIG_BF54x)
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/* disable self refresh by clearing SRREQ */
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P2.H = hi(EBIU_RSTCTL);
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P2.L = lo(EBIU_RSTCTL);
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R0 = [P2];
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@ -155,41 +149,6 @@ ENTRY(_start_dma_code)
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r0.h = hi(mem_DDRCTL2);
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[p0] = r0;
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ssync;
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#else
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p0.l = lo(EBIU_SDRRC);
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p0.h = hi(EBIU_SDRRC);
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r0 = mem_SDRRC;
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w[p0] = r0.l;
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ssync;
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p0.l = LO(EBIU_SDBCTL);
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p0.h = HI(EBIU_SDBCTL); /* SDRAM Memory Bank Control Register */
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r0 = mem_SDBCTL;
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w[p0] = r0.l;
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ssync;
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P2.H = hi(EBIU_SDGCTL);
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P2.L = lo(EBIU_SDGCTL);
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R0 = [P2];
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BITCLR (R0, 24);
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p0.h = hi(EBIU_SDSTAT);
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p0.l = lo(EBIU_SDSTAT);
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r2.l = w[p0];
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cc = bittst(r2,3);
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if !cc jump .Lskip;
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NOP;
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BITSET (R0, 23);
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.Lskip:
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[P2] = R0;
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SSYNC;
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R0.L = lo(mem_SDGCTL);
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R0.H = hi(mem_SDGCTL);
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R1 = [p2];
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R1 = R1 | R0;
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[P2] = R1;
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SSYNC;
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#endif
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RTS;
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ENDPROC(_start_dma_code)
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