USB: EHCI: remove PORT_RWC_BITS when clearing USB_PORT_FEAT_ENABLE
In the ClearPortFeature/USB_PORT_FEAT_ENABLE case, ehci_hub_control() would read from status_reg, clear PORT_PE, and write the result back to status_reg. This would clear any bits in PORT_RWC_BITS that were set in the registers. Fix this by masking these bits off before the write. Since this masking is common across all ClearPortFeature cases, move it into a single early location to avoid duplicating it. Remove the same bugfix from ehci-tegra.c's tegra_ehci_hub_control(), now that this case is correctly handled by the core. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Alan Stern <stern@rowland.harvard.edu> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -704,6 +704,7 @@ static int ehci_hub_control (
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goto error;
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wIndex--;
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temp = ehci_readl(ehci, status_reg);
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temp &= ~PORT_RWC_BITS;
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/*
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* Even if OWNER is set, so the port is owned by the
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@ -717,8 +718,7 @@ static int ehci_hub_control (
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ehci_writel(ehci, temp & ~PORT_PE, status_reg);
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break;
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case USB_PORT_FEAT_C_ENABLE:
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ehci_writel(ehci, (temp & ~PORT_RWC_BITS) | PORT_PEC,
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status_reg);
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ehci_writel(ehci, temp | PORT_PEC, status_reg);
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break;
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case USB_PORT_FEAT_SUSPEND:
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if (temp & PORT_RESET)
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@ -747,7 +747,7 @@ static int ehci_hub_control (
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spin_lock_irqsave(&ehci->lock, flags);
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}
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/* resume signaling for 20 msec */
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temp &= ~(PORT_RWC_BITS | PORT_WAKE_BITS);
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temp &= ~PORT_WAKE_BITS;
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ehci_writel(ehci, temp | PORT_RESUME, status_reg);
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ehci->reset_done[wIndex] = jiffies
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+ msecs_to_jiffies(20);
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@ -757,9 +757,8 @@ static int ehci_hub_control (
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break;
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case USB_PORT_FEAT_POWER:
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if (HCS_PPC (ehci->hcs_params))
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ehci_writel(ehci,
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temp & ~(PORT_RWC_BITS | PORT_POWER),
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status_reg);
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ehci_writel(ehci, temp & ~PORT_POWER,
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status_reg);
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break;
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case USB_PORT_FEAT_C_CONNECTION:
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if (ehci->has_lpm) {
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@ -767,12 +766,10 @@ static int ehci_hub_control (
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temp &= ~PORT_LPM;
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temp &= ~PORT_DEV_ADDR;
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}
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ehci_writel(ehci, (temp & ~PORT_RWC_BITS) | PORT_CSC,
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status_reg);
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ehci_writel(ehci, temp | PORT_CSC, status_reg);
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break;
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case USB_PORT_FEAT_C_OVER_CURRENT:
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ehci_writel(ehci, (temp & ~PORT_RWC_BITS) | PORT_OCC,
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status_reg);
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ehci_writel(ehci, temp | PORT_OCC, status_reg);
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break;
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case USB_PORT_FEAT_C_RESET:
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/* GetPortStatus clears reset */
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@ -148,18 +148,7 @@ static int tegra_ehci_hub_control(
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spin_lock_irqsave(&ehci->lock, flags);
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/*
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* In ehci_hub_control() for USB_PORT_FEAT_ENABLE clears the other bits
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* that are write on clear, by writing back the register read value, so
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* USB_PORT_FEAT_ENABLE is handled by masking the set on clear bits
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*/
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if (typeReq == ClearPortFeature && wValue == USB_PORT_FEAT_ENABLE) {
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temp = ehci_readl(ehci, status_reg) & ~PORT_RWC_BITS;
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ehci_writel(ehci, temp & ~PORT_PE, status_reg);
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goto done;
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}
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else if (typeReq == GetPortStatus) {
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if (typeReq == GetPortStatus) {
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temp = ehci_readl(ehci, status_reg);
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if (tegra->port_resuming && !(temp & PORT_SUSPEND)) {
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/* Resume completed, re-enable disconnect detection */
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