drm/nv50/gr: refactor initialisation
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Ben Skeggs
parent
8c06e60ed4
commit
6d6538a0c3
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@ -120,70 +120,62 @@ nv50_graph_unload_context(struct drm_device *dev)
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return 0;
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}
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static void
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nv50_graph_init_reset(struct drm_device *dev)
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{
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uint32_t pmc_e = NV_PMC_ENABLE_PGRAPH | (1 << 21);
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NV_DEBUG(dev, "\n");
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nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) & ~pmc_e);
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nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) | pmc_e);
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}
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static void
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nv50_graph_init_intr(struct drm_device *dev)
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{
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NV_DEBUG(dev, "\n");
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nv_wr32(dev, NV03_PGRAPH_INTR, 0xffffffff);
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nv_wr32(dev, 0x400138, 0xffffffff);
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nv_wr32(dev, NV40_PGRAPH_INTR_EN, 0xffffffff);
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}
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static void
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nv50_graph_init_regs__nv(struct drm_device *dev)
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static int
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nv50_graph_init(struct drm_device *dev, int engine)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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uint32_t units = nv_rd32(dev, 0x1540);
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struct nv50_graph_engine *pgraph = nv_engine(dev, engine);
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u32 units = nv_rd32(dev, 0x001540);
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int i;
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NV_DEBUG(dev, "\n");
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/* master reset */
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nv_mask(dev, 0x000200, 0x00200100, 0x00000000);
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nv_mask(dev, 0x000200, 0x00200100, 0x00200100);
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nv_wr32(dev, 0x40008c, 0x00000004); /* HW_CTX_SWITCH_ENABLED */
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/* reset/enable traps and interrupts */
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nv_wr32(dev, 0x400804, 0xc0000000);
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nv_wr32(dev, 0x406800, 0xc0000000);
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nv_wr32(dev, 0x400c04, 0xc0000000);
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nv_wr32(dev, 0x401800, 0xc0000000);
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nv_wr32(dev, 0x405018, 0xc0000000);
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nv_wr32(dev, 0x402000, 0xc0000000);
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for (i = 0; i < 16; i++) {
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if (units & 1 << i) {
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if (dev_priv->chipset < 0xa0) {
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nv_wr32(dev, 0x408900 + (i << 12), 0xc0000000);
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nv_wr32(dev, 0x408e08 + (i << 12), 0xc0000000);
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nv_wr32(dev, 0x408314 + (i << 12), 0xc0000000);
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} else {
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nv_wr32(dev, 0x408600 + (i << 11), 0xc0000000);
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nv_wr32(dev, 0x408708 + (i << 11), 0xc0000000);
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nv_wr32(dev, 0x40831c + (i << 11), 0xc0000000);
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}
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if (!(units & (1 << i)))
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continue;
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if (dev_priv->chipset < 0xa0) {
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nv_wr32(dev, 0x408900 + (i << 12), 0xc0000000);
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nv_wr32(dev, 0x408e08 + (i << 12), 0xc0000000);
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nv_wr32(dev, 0x408314 + (i << 12), 0xc0000000);
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} else {
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nv_wr32(dev, 0x408600 + (i << 11), 0xc0000000);
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nv_wr32(dev, 0x408708 + (i << 11), 0xc0000000);
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nv_wr32(dev, 0x40831c + (i << 11), 0xc0000000);
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}
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}
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nv_wr32(dev, 0x400108, 0xffffffff);
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nv_wr32(dev, 0x400824, 0x00004000);
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nv_wr32(dev, 0x400138, 0xffffffff);
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nv_wr32(dev, 0x400100, 0xffffffff);
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nv_wr32(dev, 0x40013c, 0xffffffff);
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nv_wr32(dev, 0x400500, 0x00010001);
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}
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static void
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nv50_graph_init_zcull(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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int i;
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NV_DEBUG(dev, "\n");
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/* upload context program, initialise ctxctl defaults */
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nv_wr32(dev, 0x400324, 0x00000000);
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for (i = 0; i < pgraph->ctxprog_size; i++)
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nv_wr32(dev, 0x400328, pgraph->ctxprog[i]);
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nv_wr32(dev, 0x400824, 0x00000000);
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nv_wr32(dev, 0x400828, 0x00000000);
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nv_wr32(dev, 0x40082c, 0x00000000);
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nv_wr32(dev, 0x400830, 0x00000000);
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nv_wr32(dev, 0x400724, 0x00000000);
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nv_wr32(dev, 0x40032c, 0x00000000);
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nv_wr32(dev, 0x400320, 4); /* CTXCTL_CMD = NEWCTXDMA */
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/* some unknown zcull magic */
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switch (dev_priv->chipset & 0xf0) {
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case 0x50:
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case 0x80:
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@ -212,43 +204,7 @@ nv50_graph_init_zcull(struct drm_device *dev)
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nv_wr32(dev, 0x402c28 + (i * 8), 0x00000000);
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nv_wr32(dev, 0x402c2c + (i * 8), 0x00000000);
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}
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}
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static int
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nv50_graph_init_ctxctl(struct drm_device *dev)
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{
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struct nv50_graph_engine *pgraph = nv_engine(dev, NVOBJ_ENGINE_GR);
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int i;
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NV_DEBUG(dev, "\n");
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nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);
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for (i = 0; i < pgraph->ctxprog_size; i++)
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nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA, pgraph->ctxprog[i]);
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nv_wr32(dev, 0x40008c, 0x00000004); /* HW_CTX_SWITCH_ENABLED */
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nv_wr32(dev, 0x400320, 4);
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nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, 0);
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nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, 0);
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return 0;
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}
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static int
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nv50_graph_init(struct drm_device *dev, int engine)
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{
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int ret;
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NV_DEBUG(dev, "\n");
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nv50_graph_init_reset(dev);
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nv50_graph_init_regs__nv(dev);
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nv50_graph_init_zcull(dev);
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ret = nv50_graph_init_ctxctl(dev);
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if (ret)
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return ret;
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nv50_graph_init_intr(dev);
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return 0;
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}
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