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RISC-V: Disable preemption before enabling interrupts 

Currently, irq is enabled before preemption disabling happens.
If the scheduler fired right here and cpu is scheduled then it
may blow up.

Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
[Atish: Commit text and code comment formatting update]
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
hifive-unleashed-5.1
Atish Patra 2018-10-02 12:14:58 -07:00 committed by Palmer Dabbelt
parent b18d6f0525
commit 6db170ff4c
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GPG Key ID: EF4CA1502CCBAB41
1 changed files with 5 additions and 1 deletions
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6
arch/riscv/kernel/smpboot.c
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@ -111,7 +111,11 @@ asmlinkage void __init smp_callin(void)
* a local TLB flush right now just in case.
*/
local_flush_tlb_all();
local_irq_enable();
/*
* Disable preemption before enabling interrupts, so we don't try to
* schedule a CPU that hasn't actually started yet.
*/
preempt_disable();
local_irq_enable();
cpu_startup_entry(CPUHP_AP_ONLINE_IDLE);
}