Merge branch 'drm-next-4.10' of git://people.freedesktop.org/~agd5f/linux into drm-fixes
- fix display regression on DCE6/8 - Powergating fixes for GFX8 - amdgpu SI fixes (golden settings, proper rev id setup, etc.) * 'drm-next-4.10' of git://people.freedesktop.org/~agd5f/linux: (21 commits) drm/amdgpu: update tile table for oland/hainan drm/amdgpu: update tile table for verde drm/amdgpu: update rev id for verde drm/amdgpu: update golden setting for verde drm/amdgpu: update rev id for oland drm/amdgpu: update golden setting for oland drm/amdgpu: update rev id for hainan drm/amdgpu: update golden setting for hainan drm/amdgpu: update rev id for pitcairn drm/amdgpu: update golden setting for pitcairn drm/amdgpu: update golden setting/tiling table of tahiti drm/amdgpu: fix cursor setting of dce6/dce8 drm/amdgpu: refine set clock gating for tonga/polaris drm/amdgpu: initialize cg flags for tonga/polaris10/polaris11. drm/amdgpu: add new gfx cg flags. drm/amdgpu: fix pg can't be disabled by PG mask. drm/amdgpu: always initialize gfx pg for gfx_v8.0. drm/amdgpu: enable AMD_PG_SUPPORT_CP in Carrizo/Stoney. drm/amdgpu: fix init save/restore list in gfx_v8.0 drm/amdgpu: fix enable_cp_power_gating in gfx_v8.0. ...hifive-unleashed-5.1
Dave Airlie
commit
6df383cf90
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@ -1944,9 +1944,7 @@ static int dce_v6_0_crtc_cursor_set2(struct drm_crtc *crtc,
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dce_v6_0_lock_cursor(crtc, true);
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if (width != amdgpu_crtc->cursor_width ||
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height != amdgpu_crtc->cursor_height ||
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hot_x != amdgpu_crtc->cursor_hot_x ||
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if (hot_x != amdgpu_crtc->cursor_hot_x ||
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hot_y != amdgpu_crtc->cursor_hot_y) {
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int x, y;
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@ -1955,8 +1953,6 @@ static int dce_v6_0_crtc_cursor_set2(struct drm_crtc *crtc,
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dce_v6_0_cursor_move_locked(crtc, x, y);
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amdgpu_crtc->cursor_width = width;
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amdgpu_crtc->cursor_height = height;
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amdgpu_crtc->cursor_hot_x = hot_x;
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amdgpu_crtc->cursor_hot_y = hot_y;
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}
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@ -2438,8 +2438,6 @@ static int dce_v8_0_crtc_cursor_set2(struct drm_crtc *crtc,
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dce_v8_0_cursor_move_locked(crtc, x, y);
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amdgpu_crtc->cursor_width = width;
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amdgpu_crtc->cursor_height = height;
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amdgpu_crtc->cursor_hot_x = hot_x;
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amdgpu_crtc->cursor_hot_y = hot_y;
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}
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File diff suppressed because it is too large
Load Diff
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@ -3949,8 +3949,12 @@ static int gfx_v8_0_init_save_restore_list(struct amdgpu_device *adev)
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temp = mmRLC_SRM_INDEX_CNTL_ADDR_0;
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data = mmRLC_SRM_INDEX_CNTL_DATA_0;
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for (i = 0; i < sizeof(unique_indices) / sizeof(int); i++) {
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amdgpu_mm_wreg(adev, temp + i, unique_indices[i] & 0x3FFFF, false);
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amdgpu_mm_wreg(adev, data + i, unique_indices[i] >> 20, false);
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if (unique_indices[i] != 0) {
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amdgpu_mm_wreg(adev, temp + i,
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unique_indices[i] & 0x3FFFF, false);
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amdgpu_mm_wreg(adev, data + i,
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unique_indices[i] >> 20, false);
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}
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}
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kfree(register_list_format);
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@ -3966,20 +3970,17 @@ static void gfx_v8_0_init_power_gating(struct amdgpu_device *adev)
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{
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uint32_t data;
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if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
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AMD_PG_SUPPORT_GFX_SMG |
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AMD_PG_SUPPORT_GFX_DMG)) {
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WREG32_FIELD(CP_RB_WPTR_POLL_CNTL, IDLE_POLL_COUNT, 0x60);
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WREG32_FIELD(CP_RB_WPTR_POLL_CNTL, IDLE_POLL_COUNT, 0x60);
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data = REG_SET_FIELD(0, RLC_PG_DELAY, POWER_UP_DELAY, 0x10);
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data = REG_SET_FIELD(data, RLC_PG_DELAY, POWER_DOWN_DELAY, 0x10);
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data = REG_SET_FIELD(data, RLC_PG_DELAY, CMD_PROPAGATE_DELAY, 0x10);
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data = REG_SET_FIELD(data, RLC_PG_DELAY, MEM_SLEEP_DELAY, 0x10);
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WREG32(mmRLC_PG_DELAY, data);
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data = REG_SET_FIELD(0, RLC_PG_DELAY, POWER_UP_DELAY, 0x10);
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data = REG_SET_FIELD(data, RLC_PG_DELAY, POWER_DOWN_DELAY, 0x10);
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data = REG_SET_FIELD(data, RLC_PG_DELAY, CMD_PROPAGATE_DELAY, 0x10);
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data = REG_SET_FIELD(data, RLC_PG_DELAY, MEM_SLEEP_DELAY, 0x10);
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WREG32(mmRLC_PG_DELAY, data);
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WREG32_FIELD(RLC_PG_DELAY_2, SERDES_CMD_DELAY, 0x3);
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WREG32_FIELD(RLC_AUTO_PG_CTRL, GRBM_REG_SAVE_GFX_IDLE_THRESHOLD, 0x55f0);
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WREG32_FIELD(RLC_PG_DELAY_2, SERDES_CMD_DELAY, 0x3);
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WREG32_FIELD(RLC_AUTO_PG_CTRL, GRBM_REG_SAVE_GFX_IDLE_THRESHOLD, 0x55f0);
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}
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}
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static void cz_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev,
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@ -3996,41 +3997,37 @@ static void cz_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev,
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static void cz_enable_cp_power_gating(struct amdgpu_device *adev, bool enable)
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{
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WREG32_FIELD(RLC_PG_CNTL, CP_PG_DISABLE, enable ? 1 : 0);
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WREG32_FIELD(RLC_PG_CNTL, CP_PG_DISABLE, enable ? 0 : 1);
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}
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static void gfx_v8_0_init_pg(struct amdgpu_device *adev)
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{
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if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
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AMD_PG_SUPPORT_GFX_SMG |
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AMD_PG_SUPPORT_GFX_DMG |
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AMD_PG_SUPPORT_CP |
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AMD_PG_SUPPORT_GDS |
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AMD_PG_SUPPORT_RLC_SMU_HS)) {
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if ((adev->asic_type == CHIP_CARRIZO) ||
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(adev->asic_type == CHIP_STONEY)) {
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gfx_v8_0_init_csb(adev);
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gfx_v8_0_init_save_restore_list(adev);
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gfx_v8_0_enable_save_restore_machine(adev);
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if ((adev->asic_type == CHIP_CARRIZO) ||
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(adev->asic_type == CHIP_STONEY)) {
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WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8);
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gfx_v8_0_init_power_gating(adev);
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WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask);
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if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
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cz_enable_sck_slow_down_on_power_up(adev, true);
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cz_enable_sck_slow_down_on_power_down(adev, true);
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} else {
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cz_enable_sck_slow_down_on_power_up(adev, false);
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cz_enable_sck_slow_down_on_power_down(adev, false);
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}
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if (adev->pg_flags & AMD_PG_SUPPORT_CP)
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cz_enable_cp_power_gating(adev, true);
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else
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cz_enable_cp_power_gating(adev, false);
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} else if (adev->asic_type == CHIP_POLARIS11) {
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gfx_v8_0_init_power_gating(adev);
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WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8);
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gfx_v8_0_init_power_gating(adev);
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WREG32(mmRLC_PG_ALWAYS_ON_CU_MASK, adev->gfx.cu_info.ao_cu_mask);
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if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
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cz_enable_sck_slow_down_on_power_up(adev, true);
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cz_enable_sck_slow_down_on_power_down(adev, true);
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} else {
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cz_enable_sck_slow_down_on_power_up(adev, false);
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cz_enable_sck_slow_down_on_power_down(adev, false);
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}
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if (adev->pg_flags & AMD_PG_SUPPORT_CP)
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cz_enable_cp_power_gating(adev, true);
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else
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cz_enable_cp_power_gating(adev, false);
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} else if (adev->asic_type == CHIP_POLARIS11) {
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gfx_v8_0_init_csb(adev);
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gfx_v8_0_init_save_restore_list(adev);
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gfx_v8_0_enable_save_restore_machine(adev);
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gfx_v8_0_init_power_gating(adev);
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}
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}
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static void gfx_v8_0_rlc_stop(struct amdgpu_device *adev)
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@ -5339,14 +5336,11 @@ static int gfx_v8_0_set_powergating_state(void *handle,
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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bool enable = (state == AMD_PG_STATE_GATE) ? true : false;
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if (!(adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
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return 0;
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switch (adev->asic_type) {
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case CHIP_CARRIZO:
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case CHIP_STONEY:
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if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)
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cz_update_gfx_cg_power_gating(adev, enable);
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cz_update_gfx_cg_power_gating(adev, enable);
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if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable)
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gfx_v8_0_enable_gfx_static_mg_power_gating(adev, true);
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@ -5791,25 +5785,49 @@ static int gfx_v8_0_update_gfx_clock_gating(struct amdgpu_device *adev,
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static int gfx_v8_0_tonga_update_gfx_clock_gating(struct amdgpu_device *adev,
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enum amd_clockgating_state state)
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{
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uint32_t msg_id, pp_state;
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uint32_t msg_id, pp_state = 0;
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uint32_t pp_support_state = 0;
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void *pp_handle = adev->powerplay.pp_handle;
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if (state == AMD_CG_STATE_UNGATE)
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pp_state = 0;
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else
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pp_state = PP_STATE_CG | PP_STATE_LS;
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if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS)) {
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if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) {
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pp_support_state = PP_STATE_SUPPORT_LS;
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pp_state = PP_STATE_LS;
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}
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if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) {
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pp_support_state |= PP_STATE_SUPPORT_CG;
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pp_state |= PP_STATE_CG;
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}
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if (state == AMD_CG_STATE_UNGATE)
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pp_state = 0;
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msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
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PP_BLOCK_GFX_CG,
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PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
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pp_state);
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amd_set_clockgating_by_smu(pp_handle, msg_id);
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msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
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PP_BLOCK_GFX_CG,
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pp_support_state,
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pp_state);
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amd_set_clockgating_by_smu(pp_handle, msg_id);
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}
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msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
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PP_BLOCK_GFX_MG,
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PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
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pp_state);
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amd_set_clockgating_by_smu(pp_handle, msg_id);
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if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)) {
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if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
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pp_support_state = PP_STATE_SUPPORT_LS;
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pp_state = PP_STATE_LS;
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}
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if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) {
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pp_support_state |= PP_STATE_SUPPORT_CG;
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pp_state |= PP_STATE_CG;
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}
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if (state == AMD_CG_STATE_UNGATE)
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pp_state = 0;
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msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
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PP_BLOCK_GFX_MG,
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pp_support_state,
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pp_state);
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amd_set_clockgating_by_smu(pp_handle, msg_id);
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}
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return 0;
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}
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@ -5817,43 +5835,98 @@ static int gfx_v8_0_tonga_update_gfx_clock_gating(struct amdgpu_device *adev,
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static int gfx_v8_0_polaris_update_gfx_clock_gating(struct amdgpu_device *adev,
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enum amd_clockgating_state state)
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{
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uint32_t msg_id, pp_state;
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uint32_t msg_id, pp_state = 0;
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uint32_t pp_support_state = 0;
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void *pp_handle = adev->powerplay.pp_handle;
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if (state == AMD_CG_STATE_UNGATE)
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pp_state = 0;
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else
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pp_state = PP_STATE_CG | PP_STATE_LS;
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if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_CGLS)) {
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if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) {
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pp_support_state = PP_STATE_SUPPORT_LS;
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pp_state = PP_STATE_LS;
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}
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if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) {
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pp_support_state |= PP_STATE_SUPPORT_CG;
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pp_state |= PP_STATE_CG;
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}
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if (state == AMD_CG_STATE_UNGATE)
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pp_state = 0;
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msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
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PP_BLOCK_GFX_CG,
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PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
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pp_state);
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amd_set_clockgating_by_smu(pp_handle, msg_id);
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msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
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PP_BLOCK_GFX_CG,
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pp_support_state,
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pp_state);
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amd_set_clockgating_by_smu(pp_handle, msg_id);
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}
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msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
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PP_BLOCK_GFX_3D,
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PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
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pp_state);
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amd_set_clockgating_by_smu(pp_handle, msg_id);
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if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_3D_CGCG | AMD_CG_SUPPORT_GFX_3D_CGLS)) {
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if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) {
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pp_support_state = PP_STATE_SUPPORT_LS;
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pp_state = PP_STATE_LS;
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}
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if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) {
|
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pp_support_state |= PP_STATE_SUPPORT_CG;
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pp_state |= PP_STATE_CG;
|
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}
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if (state == AMD_CG_STATE_UNGATE)
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pp_state = 0;
|
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|
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msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
|
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PP_BLOCK_GFX_MG,
|
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PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
|
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pp_state);
|
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amd_set_clockgating_by_smu(pp_handle, msg_id);
|
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msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
|
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PP_BLOCK_GFX_3D,
|
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pp_support_state,
|
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pp_state);
|
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amd_set_clockgating_by_smu(pp_handle, msg_id);
|
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}
|
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|
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msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
|
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PP_BLOCK_GFX_RLC,
|
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PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
|
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pp_state);
|
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amd_set_clockgating_by_smu(pp_handle, msg_id);
|
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if (adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)) {
|
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if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
|
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pp_support_state = PP_STATE_SUPPORT_LS;
|
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pp_state = PP_STATE_LS;
|
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}
|
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|
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msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
|
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if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) {
|
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pp_support_state |= PP_STATE_SUPPORT_CG;
|
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pp_state |= PP_STATE_CG;
|
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}
|
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|
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if (state == AMD_CG_STATE_UNGATE)
|
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pp_state = 0;
|
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|
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msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
|
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PP_BLOCK_GFX_MG,
|
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pp_support_state,
|
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pp_state);
|
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amd_set_clockgating_by_smu(pp_handle, msg_id);
|
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}
|
||||
|
||||
if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
|
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pp_support_state = PP_STATE_SUPPORT_LS;
|
||||
|
||||
if (state == AMD_CG_STATE_UNGATE)
|
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pp_state = 0;
|
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else
|
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pp_state = PP_STATE_LS;
|
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|
||||
msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
|
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PP_BLOCK_GFX_RLC,
|
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pp_support_state,
|
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pp_state);
|
||||
amd_set_clockgating_by_smu(pp_handle, msg_id);
|
||||
}
|
||||
|
||||
if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
|
||||
pp_support_state = PP_STATE_SUPPORT_LS;
|
||||
|
||||
if (state == AMD_CG_STATE_UNGATE)
|
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pp_state = 0;
|
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else
|
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pp_state = PP_STATE_LS;
|
||||
msg_id = PP_CG_MSG_ID(PP_GROUP_GFX,
|
||||
PP_BLOCK_GFX_CP,
|
||||
PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
|
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pp_support_state,
|
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pp_state);
|
||||
amd_set_clockgating_by_smu(pp_handle, msg_id);
|
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amd_set_clockgating_by_smu(pp_handle, msg_id);
|
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}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -43,13 +43,14 @@
|
|||
|
||||
static const u32 tahiti_golden_registers[] =
|
||||
{
|
||||
0x17bc, 0x00000030, 0x00000011,
|
||||
0x2684, 0x00010000, 0x00018208,
|
||||
0x260c, 0xffffffff, 0x00000000,
|
||||
0x260d, 0xf00fffff, 0x00000400,
|
||||
0x260e, 0x0002021c, 0x00020200,
|
||||
0x031e, 0x00000080, 0x00000000,
|
||||
0x340c, 0x000300c0, 0x00800040,
|
||||
0x360c, 0x000300c0, 0x00800040,
|
||||
0x340c, 0x000000c0, 0x00800040,
|
||||
0x360c, 0x000000c0, 0x00800040,
|
||||
0x16ec, 0x000000f0, 0x00000070,
|
||||
0x16f0, 0x00200000, 0x50100000,
|
||||
0x1c0c, 0x31000311, 0x00000011,
|
||||
|
|
@ -60,7 +61,7 @@ static const u32 tahiti_golden_registers[] =
|
|||
0x22c4, 0x0000ff0f, 0x00000000,
|
||||
0xa293, 0x07ffffff, 0x4e000000,
|
||||
0xa0d4, 0x3f3f3fff, 0x2a00126a,
|
||||
0x000c, 0x000000ff, 0x0040,
|
||||
0x000c, 0xffffffff, 0x0040,
|
||||
0x000d, 0x00000040, 0x00004040,
|
||||
0x2440, 0x07ffffff, 0x03000000,
|
||||
0x23a2, 0x01ff1f3f, 0x00000000,
|
||||
|
|
@ -73,7 +74,11 @@ static const u32 tahiti_golden_registers[] =
|
|||
0x2234, 0xffffffff, 0x000fff40,
|
||||
0x2235, 0x0000001f, 0x00000010,
|
||||
0x0504, 0x20000000, 0x20fffed8,
|
||||
0x0570, 0x000c0fc0, 0x000c0400
|
||||
0x0570, 0x000c0fc0, 0x000c0400,
|
||||
0x052c, 0x0fffffff, 0xffffffff,
|
||||
0x052d, 0x0fffffff, 0x0fffffff,
|
||||
0x052e, 0x0fffffff, 0x0fffffff,
|
||||
0x052f, 0x0fffffff, 0x0fffffff
|
||||
};
|
||||
|
||||
static const u32 tahiti_golden_registers2[] =
|
||||
|
|
@ -83,16 +88,18 @@ static const u32 tahiti_golden_registers2[] =
|
|||
|
||||
static const u32 tahiti_golden_rlc_registers[] =
|
||||
{
|
||||
0x263e, 0xffffffff, 0x12011003,
|
||||
0x3109, 0xffffffff, 0x00601005,
|
||||
0x311f, 0xffffffff, 0x10104040,
|
||||
0x3122, 0xffffffff, 0x0100000a,
|
||||
0x30c5, 0xffffffff, 0x00000800,
|
||||
0x30c3, 0xffffffff, 0x800000f4,
|
||||
0x3d2a, 0xffffffff, 0x00000000
|
||||
0x3d2a, 0x00000008, 0x00000000
|
||||
};
|
||||
|
||||
static const u32 pitcairn_golden_registers[] =
|
||||
{
|
||||
0x17bc, 0x00000030, 0x00000011,
|
||||
0x2684, 0x00010000, 0x00018208,
|
||||
0x260c, 0xffffffff, 0x00000000,
|
||||
0x260d, 0xf00fffff, 0x00000400,
|
||||
|
|
@ -110,7 +117,7 @@ static const u32 pitcairn_golden_registers[] =
|
|||
0x22c4, 0x0000ff0f, 0x00000000,
|
||||
0xa293, 0x07ffffff, 0x4e000000,
|
||||
0xa0d4, 0x3f3f3fff, 0x2a00126a,
|
||||
0x000c, 0x000000ff, 0x0040,
|
||||
0x000c, 0xffffffff, 0x0040,
|
||||
0x000d, 0x00000040, 0x00004040,
|
||||
0x2440, 0x07ffffff, 0x03000000,
|
||||
0x2418, 0x0000007f, 0x00000020,
|
||||
|
|
@ -119,11 +126,16 @@ static const u32 pitcairn_golden_registers[] =
|
|||
0x2b04, 0xffffffff, 0x00000000,
|
||||
0x2b03, 0xffffffff, 0x32761054,
|
||||
0x2235, 0x0000001f, 0x00000010,
|
||||
0x0570, 0x000c0fc0, 0x000c0400
|
||||
0x0570, 0x000c0fc0, 0x000c0400,
|
||||
0x052c, 0x0fffffff, 0xffffffff,
|
||||
0x052d, 0x0fffffff, 0x0fffffff,
|
||||
0x052e, 0x0fffffff, 0x0fffffff,
|
||||
0x052f, 0x0fffffff, 0x0fffffff
|
||||
};
|
||||
|
||||
static const u32 pitcairn_golden_rlc_registers[] =
|
||||
{
|
||||
0x263e, 0xffffffff, 0x12011003,
|
||||
0x3109, 0xffffffff, 0x00601004,
|
||||
0x311f, 0xffffffff, 0x10102020,
|
||||
0x3122, 0xffffffff, 0x01000020,
|
||||
|
|
@ -133,133 +145,134 @@ static const u32 pitcairn_golden_rlc_registers[] =
|
|||
|
||||
static const u32 verde_pg_init[] =
|
||||
{
|
||||
0xd4f, 0xffffffff, 0x40000,
|
||||
0xd4e, 0xffffffff, 0x200010ff,
|
||||
0xd4f, 0xffffffff, 0x0,
|
||||
0xd4f, 0xffffffff, 0x0,
|
||||
0xd4f, 0xffffffff, 0x0,
|
||||
0xd4f, 0xffffffff, 0x0,
|
||||
0xd4f, 0xffffffff, 0x0,
|
||||
0xd4f, 0xffffffff, 0x7007,
|
||||
0xd4e, 0xffffffff, 0x300010ff,
|
||||
0xd4f, 0xffffffff, 0x0,
|
||||
0xd4f, 0xffffffff, 0x0,
|
||||
0xd4f, 0xffffffff, 0x0,
|
||||
0xd4f, 0xffffffff, 0x0,
|
||||
0xd4f, 0xffffffff, 0x0,
|
||||
0xd4f, 0xffffffff, 0x400000,
|
||||
0xd4e, 0xffffffff, 0x100010ff,
|
||||
0xd4f, 0xffffffff, 0x0,
|
||||
0xd4f, 0xffffffff, 0x0,
|
||||
0xd4f, 0xffffffff, 0x0,
|
||||
0xd4f, 0xffffffff, 0x0,
|
||||
0xd4f, 0xffffffff, 0x0,
|
||||
0xd4f, 0xffffffff, 0x120200,
|
||||
0xd4e, 0xffffffff, 0x500010ff,
|
||||
0xd4f, 0xffffffff, 0x0,
|
||||
0xd4f, 0xffffffff, 0x0,
|
||||
0xd4f, 0xffffffff, 0x0,
|
||||
0xd4f, 0xffffffff, 0x0,
|
||||
0xd4f, 0xffffffff, 0x0,
|
||||
0xd4f, 0xffffffff, 0x1e1e16,
|
||||
0xd4e, 0xffffffff, 0x600010ff,
|
||||
0xd4f, 0xffffffff, 0x0,
|
||||
0xd4f, 0xffffffff, 0x0,
|
||||
0xd4f, 0xffffffff, 0x0,
|
||||
0xd4f, 0xffffffff, 0x0,
|
||||
0xd4f, 0xffffffff, 0x0,
|
||||
0xd4f, 0xffffffff, 0x171f1e,
|
||||
0xd4e, 0xffffffff, 0x700010ff,
|
||||
0xd4f, 0xffffffff, 0x0,
|
||||
0xd4f, 0xffffffff, 0x0,
|
||||
0xd4f, 0xffffffff, 0x0,
|
||||
0xd4f, 0xffffffff, 0x0,
|
||||
0xd4f, 0xffffffff, 0x0,
|
||||
0xd4f, 0xffffffff, 0x0,
|
||||
0xd4e, 0xffffffff, 0x9ff,
|
||||
0xd40, 0xffffffff, 0x0,
|
||||
0xd41, 0xffffffff, 0x10000800,
|
||||
0xd41, 0xffffffff, 0xf,
|
||||
0xd41, 0xffffffff, 0xf,
|
||||
0xd40, 0xffffffff, 0x4,
|
||||
0xd41, 0xffffffff, 0x1000051e,
|
||||
0xd41, 0xffffffff, 0xffff,
|
||||
0xd41, 0xffffffff, 0xffff,
|
||||
0xd40, 0xffffffff, 0x8,
|
||||
0xd41, 0xffffffff, 0x80500,
|
||||
0xd40, 0xffffffff, 0x12,
|
||||
0xd41, 0xffffffff, 0x9050c,
|
||||
0xd40, 0xffffffff, 0x1d,
|
||||
0xd41, 0xffffffff, 0xb052c,
|
||||
0xd40, 0xffffffff, 0x2a,
|
||||
0xd41, 0xffffffff, 0x1053e,
|
||||
0xd40, 0xffffffff, 0x2d,
|
||||
0xd41, 0xffffffff, 0x10546,
|
||||
0xd40, 0xffffffff, 0x30,
|
||||
0xd41, 0xffffffff, 0xa054e,
|
||||
0xd40, 0xffffffff, 0x3c,
|
||||
0xd41, 0xffffffff, 0x1055f,
|
||||
0xd40, 0xffffffff, 0x3f,
|
||||
0xd41, 0xffffffff, 0x10567,
|
||||
0xd40, 0xffffffff, 0x42,
|
||||
0xd41, 0xffffffff, 0x1056f,
|
||||
0xd40, 0xffffffff, 0x45,
|
||||
0xd41, 0xffffffff, 0x10572,
|
||||
0xd40, 0xffffffff, 0x48,
|
||||
0xd41, 0xffffffff, 0x20575,
|
||||
0xd40, 0xffffffff, 0x4c,
|
||||
0xd41, 0xffffffff, 0x190801,
|
||||
0xd40, 0xffffffff, 0x67,
|
||||
0xd41, 0xffffffff, 0x1082a,
|
||||
0xd40, 0xffffffff, 0x6a,
|
||||
0xd41, 0xffffffff, 0x1b082d,
|
||||
0xd40, 0xffffffff, 0x87,
|
||||
0xd41, 0xffffffff, 0x310851,
|
||||
0xd40, 0xffffffff, 0xba,
|
||||
0xd41, 0xffffffff, 0x891,
|
||||
0xd40, 0xffffffff, 0xbc,
|
||||
0xd41, 0xffffffff, 0x893,
|
||||
0xd40, 0xffffffff, 0xbe,
|
||||
0xd41, 0xffffffff, 0x20895,
|
||||
0xd40, 0xffffffff, 0xc2,
|
||||
0xd41, 0xffffffff, 0x20899,
|
||||
0xd40, 0xffffffff, 0xc6,
|
||||
0xd41, 0xffffffff, 0x2089d,
|
||||
0xd40, 0xffffffff, 0xca,
|
||||
0xd41, 0xffffffff, 0x8a1,
|
||||
0xd40, 0xffffffff, 0xcc,
|
||||
0xd41, 0xffffffff, 0x8a3,
|
||||
0xd40, 0xffffffff, 0xce,
|
||||
0xd41, 0xffffffff, 0x308a5,
|
||||
0xd40, 0xffffffff, 0xd3,
|
||||
0xd41, 0xffffffff, 0x6d08cd,
|
||||
0xd40, 0xffffffff, 0x142,
|
||||
0xd41, 0xffffffff, 0x2000095a,
|
||||
0xd41, 0xffffffff, 0x1,
|
||||
0xd40, 0xffffffff, 0x144,
|
||||
0xd41, 0xffffffff, 0x301f095b,
|
||||
0xd40, 0xffffffff, 0x165,
|
||||
0xd41, 0xffffffff, 0xc094d,
|
||||
0xd40, 0xffffffff, 0x173,
|
||||
0xd41, 0xffffffff, 0xf096d,
|
||||
0xd40, 0xffffffff, 0x184,
|
||||
0xd41, 0xffffffff, 0x15097f,
|
||||
0xd40, 0xffffffff, 0x19b,
|
||||
0xd41, 0xffffffff, 0xc0998,
|
||||
0xd40, 0xffffffff, 0x1a9,
|
||||
0xd41, 0xffffffff, 0x409a7,
|
||||
0xd40, 0xffffffff, 0x1af,
|
||||
0xd41, 0xffffffff, 0xcdc,
|
||||
0xd40, 0xffffffff, 0x1b1,
|
||||
0xd41, 0xffffffff, 0x800,
|
||||
0xd42, 0xffffffff, 0x6c9b2000,
|
||||
0xd44, 0xfc00, 0x2000,
|
||||
0xd51, 0xffffffff, 0xfc0,
|
||||
0xa35, 0x00000100, 0x100
|
||||
0x0d4f, 0xffffffff, 0x40000,
|
||||
0x0d4e, 0xffffffff, 0x200010ff,
|
||||
0x0d4f, 0xffffffff, 0x0,
|
||||
0x0d4f, 0xffffffff, 0x0,
|
||||
0x0d4f, 0xffffffff, 0x0,
|
||||
0x0d4f, 0xffffffff, 0x0,
|
||||
0x0d4f, 0xffffffff, 0x0,
|
||||
0x0d4f, 0xffffffff, 0x7007,
|
||||
0x0d4e, 0xffffffff, 0x300010ff,
|
||||
0x0d4f, 0xffffffff, 0x0,
|
||||
0x0d4f, 0xffffffff, 0x0,
|
||||
0x0d4f, 0xffffffff, 0x0,
|
||||
0x0d4f, 0xffffffff, 0x0,
|
||||
0x0d4f, 0xffffffff, 0x0,
|
||||
0x0d4f, 0xffffffff, 0x400000,
|
||||
0x0d4e, 0xffffffff, 0x100010ff,
|
||||
0x0d4f, 0xffffffff, 0x0,
|
||||
0x0d4f, 0xffffffff, 0x0,
|
||||
0x0d4f, 0xffffffff, 0x0,
|
||||
0x0d4f, 0xffffffff, 0x0,
|
||||
0x0d4f, 0xffffffff, 0x0,
|
||||
0x0d4f, 0xffffffff, 0x120200,
|
||||
0x0d4e, 0xffffffff, 0x500010ff,
|
||||
0x0d4f, 0xffffffff, 0x0,
|
||||
0x0d4f, 0xffffffff, 0x0,
|
||||
0x0d4f, 0xffffffff, 0x0,
|
||||
0x0d4f, 0xffffffff, 0x0,
|
||||
0x0d4f, 0xffffffff, 0x0,
|
||||
0x0d4f, 0xffffffff, 0x1e1e16,
|
||||
0x0d4e, 0xffffffff, 0x600010ff,
|
||||
0x0d4f, 0xffffffff, 0x0,
|
||||
0x0d4f, 0xffffffff, 0x0,
|
||||
0x0d4f, 0xffffffff, 0x0,
|
||||
0x0d4f, 0xffffffff, 0x0,
|
||||
0x0d4f, 0xffffffff, 0x0,
|
||||
0x0d4f, 0xffffffff, 0x171f1e,
|
||||
0x0d4e, 0xffffffff, 0x700010ff,
|
||||
0x0d4f, 0xffffffff, 0x0,
|
||||
0x0d4f, 0xffffffff, 0x0,
|
||||
0x0d4f, 0xffffffff, 0x0,
|
||||
0x0d4f, 0xffffffff, 0x0,
|
||||
0x0d4f, 0xffffffff, 0x0,
|
||||
0x0d4f, 0xffffffff, 0x0,
|
||||
0x0d4e, 0xffffffff, 0x9ff,
|
||||
0x0d40, 0xffffffff, 0x0,
|
||||
0x0d41, 0xffffffff, 0x10000800,
|
||||
0x0d41, 0xffffffff, 0xf,
|
||||
0x0d41, 0xffffffff, 0xf,
|
||||
0x0d40, 0xffffffff, 0x4,
|
||||
0x0d41, 0xffffffff, 0x1000051e,
|
||||
0x0d41, 0xffffffff, 0xffff,
|
||||
0x0d41, 0xffffffff, 0xffff,
|
||||
0x0d40, 0xffffffff, 0x8,
|
||||
0x0d41, 0xffffffff, 0x80500,
|
||||
0x0d40, 0xffffffff, 0x12,
|
||||
0x0d41, 0xffffffff, 0x9050c,
|
||||
0x0d40, 0xffffffff, 0x1d,
|
||||
0x0d41, 0xffffffff, 0xb052c,
|
||||
0x0d40, 0xffffffff, 0x2a,
|
||||
0x0d41, 0xffffffff, 0x1053e,
|
||||
0x0d40, 0xffffffff, 0x2d,
|
||||
0x0d41, 0xffffffff, 0x10546,
|
||||
0x0d40, 0xffffffff, 0x30,
|
||||
0x0d41, 0xffffffff, 0xa054e,
|
||||
0x0d40, 0xffffffff, 0x3c,
|
||||
0x0d41, 0xffffffff, 0x1055f,
|
||||
0x0d40, 0xffffffff, 0x3f,
|
||||
0x0d41, 0xffffffff, 0x10567,
|
||||
0x0d40, 0xffffffff, 0x42,
|
||||
0x0d41, 0xffffffff, 0x1056f,
|
||||
0x0d40, 0xffffffff, 0x45,
|
||||
0x0d41, 0xffffffff, 0x10572,
|
||||
0x0d40, 0xffffffff, 0x48,
|
||||
0x0d41, 0xffffffff, 0x20575,
|
||||
0x0d40, 0xffffffff, 0x4c,
|
||||
0x0d41, 0xffffffff, 0x190801,
|
||||
0x0d40, 0xffffffff, 0x67,
|
||||
0x0d41, 0xffffffff, 0x1082a,
|
||||
0x0d40, 0xffffffff, 0x6a,
|
||||
0x0d41, 0xffffffff, 0x1b082d,
|
||||
0x0d40, 0xffffffff, 0x87,
|
||||
0x0d41, 0xffffffff, 0x310851,
|
||||
0x0d40, 0xffffffff, 0xba,
|
||||
0x0d41, 0xffffffff, 0x891,
|
||||
0x0d40, 0xffffffff, 0xbc,
|
||||
0x0d41, 0xffffffff, 0x893,
|
||||
0x0d40, 0xffffffff, 0xbe,
|
||||
0x0d41, 0xffffffff, 0x20895,
|
||||
0x0d40, 0xffffffff, 0xc2,
|
||||
0x0d41, 0xffffffff, 0x20899,
|
||||
0x0d40, 0xffffffff, 0xc6,
|
||||
0x0d41, 0xffffffff, 0x2089d,
|
||||
0x0d40, 0xffffffff, 0xca,
|
||||
0x0d41, 0xffffffff, 0x8a1,
|
||||
0x0d40, 0xffffffff, 0xcc,
|
||||
0x0d41, 0xffffffff, 0x8a3,
|
||||
0x0d40, 0xffffffff, 0xce,
|
||||
0x0d41, 0xffffffff, 0x308a5,
|
||||
0x0d40, 0xffffffff, 0xd3,
|
||||
0x0d41, 0xffffffff, 0x6d08cd,
|
||||
0x0d40, 0xffffffff, 0x142,
|
||||
0x0d41, 0xffffffff, 0x2000095a,
|
||||
0x0d41, 0xffffffff, 0x1,
|
||||
0x0d40, 0xffffffff, 0x144,
|
||||
0x0d41, 0xffffffff, 0x301f095b,
|
||||
0x0d40, 0xffffffff, 0x165,
|
||||
0x0d41, 0xffffffff, 0xc094d,
|
||||
0x0d40, 0xffffffff, 0x173,
|
||||
0x0d41, 0xffffffff, 0xf096d,
|
||||
0x0d40, 0xffffffff, 0x184,
|
||||
0x0d41, 0xffffffff, 0x15097f,
|
||||
0x0d40, 0xffffffff, 0x19b,
|
||||
0x0d41, 0xffffffff, 0xc0998,
|
||||
0x0d40, 0xffffffff, 0x1a9,
|
||||
0x0d41, 0xffffffff, 0x409a7,
|
||||
0x0d40, 0xffffffff, 0x1af,
|
||||
0x0d41, 0xffffffff, 0xcdc,
|
||||
0x0d40, 0xffffffff, 0x1b1,
|
||||
0x0d41, 0xffffffff, 0x800,
|
||||
0x0d42, 0xffffffff, 0x6c9b2000,
|
||||
0x0d44, 0xfc00, 0x2000,
|
||||
0x0d51, 0xffffffff, 0xfc0,
|
||||
0x0a35, 0x00000100, 0x100
|
||||
};
|
||||
|
||||
static const u32 verde_golden_rlc_registers[] =
|
||||
{
|
||||
0x263e, 0xffffffff, 0x02010002,
|
||||
0x3109, 0xffffffff, 0x033f1005,
|
||||
0x311f, 0xffffffff, 0x10808020,
|
||||
0x3122, 0xffffffff, 0x00800008,
|
||||
|
|
@ -269,65 +282,45 @@ static const u32 verde_golden_rlc_registers[] =
|
|||
|
||||
static const u32 verde_golden_registers[] =
|
||||
{
|
||||
0x17bc, 0x00000030, 0x00000011,
|
||||
0x2684, 0x00010000, 0x00018208,
|
||||
0x260c, 0xffffffff, 0x00000000,
|
||||
0x260d, 0xf00fffff, 0x00000400,
|
||||
0x260e, 0x0002021c, 0x00020200,
|
||||
0x031e, 0x00000080, 0x00000000,
|
||||
0x340c, 0x000300c0, 0x00800040,
|
||||
0x340c, 0x000300c0, 0x00800040,
|
||||
0x360c, 0x000300c0, 0x00800040,
|
||||
0x360c, 0x000300c0, 0x00800040,
|
||||
0x16ec, 0x000000f0, 0x00000070,
|
||||
0x16f0, 0x00200000, 0x50100000,
|
||||
|
||||
0x1c0c, 0x31000311, 0x00000011,
|
||||
0x0ab9, 0x00073ffe, 0x000022a2,
|
||||
0x0ab9, 0x00073ffe, 0x000022a2,
|
||||
0x0ab9, 0x00073ffe, 0x000022a2,
|
||||
0x0903, 0x000007ff, 0x00000000,
|
||||
0x0903, 0x000007ff, 0x00000000,
|
||||
0x0903, 0x000007ff, 0x00000000,
|
||||
0x2285, 0xf000001f, 0x00000007,
|
||||
0x2285, 0xf000001f, 0x00000007,
|
||||
0x2285, 0xf000001f, 0x00000007,
|
||||
0x2285, 0xffffffff, 0x00ffffff,
|
||||
0x22c9, 0xffffffff, 0x00ffffff,
|
||||
0x22c4, 0x0000ff0f, 0x00000000,
|
||||
|
||||
0xa293, 0x07ffffff, 0x4e000000,
|
||||
0xa0d4, 0x3f3f3fff, 0x0000124a,
|
||||
0xa0d4, 0x3f3f3fff, 0x0000124a,
|
||||
0xa0d4, 0x3f3f3fff, 0x0000124a,
|
||||
0x000c, 0x000000ff, 0x0040,
|
||||
0x000c, 0xffffffff, 0x0040,
|
||||
0x000d, 0x00000040, 0x00004040,
|
||||
0x2440, 0x07ffffff, 0x03000000,
|
||||
0x2440, 0x07ffffff, 0x03000000,
|
||||
0x23a2, 0x01ff1f3f, 0x00000000,
|
||||
0x23a3, 0x01ff1f3f, 0x00000000,
|
||||
0x23a2, 0x01ff1f3f, 0x00000000,
|
||||
0x23a1, 0x01ff1f3f, 0x00000000,
|
||||
0x23a1, 0x01ff1f3f, 0x00000000,
|
||||
|
||||
0x23a1, 0x01ff1f3f, 0x00000000,
|
||||
0x2418, 0x0000007f, 0x00000020,
|
||||
0x2542, 0x00010000, 0x00010000,
|
||||
0x2b01, 0x000003ff, 0x00000003,
|
||||
0x2b05, 0x000003ff, 0x00000003,
|
||||
0x2b05, 0x000003ff, 0x00000003,
|
||||
0x2b04, 0xffffffff, 0x00000000,
|
||||
0x2b04, 0xffffffff, 0x00000000,
|
||||
0x2b04, 0xffffffff, 0x00000000,
|
||||
0x2b03, 0xffffffff, 0x00001032,
|
||||
0x2b03, 0xffffffff, 0x00001032,
|
||||
0x2b03, 0xffffffff, 0x00001032,
|
||||
0x2235, 0x0000001f, 0x00000010,
|
||||
0x2235, 0x0000001f, 0x00000010,
|
||||
0x2235, 0x0000001f, 0x00000010,
|
||||
0x0570, 0x000c0fc0, 0x000c0400
|
||||
0x0570, 0x000c0fc0, 0x000c0400,
|
||||
0x052c, 0x0fffffff, 0xffffffff,
|
||||
0x052d, 0x0fffffff, 0x0fffffff,
|
||||
0x052e, 0x0fffffff, 0x0fffffff,
|
||||
0x052f, 0x0fffffff, 0x0fffffff
|
||||
};
|
||||
|
||||
static const u32 oland_golden_registers[] =
|
||||
{
|
||||
0x17bc, 0x00000030, 0x00000011,
|
||||
0x2684, 0x00010000, 0x00018208,
|
||||
0x260c, 0xffffffff, 0x00000000,
|
||||
0x260d, 0xf00fffff, 0x00000400,
|
||||
|
|
@ -336,7 +329,7 @@ static const u32 oland_golden_registers[] =
|
|||
0x340c, 0x000300c0, 0x00800040,
|
||||
0x360c, 0x000300c0, 0x00800040,
|
||||
0x16ec, 0x000000f0, 0x00000070,
|
||||
0x16f9, 0x00200000, 0x50100000,
|
||||
0x16f0, 0x00200000, 0x50100000,
|
||||
0x1c0c, 0x31000311, 0x00000011,
|
||||
0x0ab9, 0x00073ffe, 0x000022a2,
|
||||
0x0903, 0x000007ff, 0x00000000,
|
||||
|
|
@ -345,7 +338,7 @@ static const u32 oland_golden_registers[] =
|
|||
0x22c4, 0x0000ff0f, 0x00000000,
|
||||
0xa293, 0x07ffffff, 0x4e000000,
|
||||
0xa0d4, 0x3f3f3fff, 0x00000082,
|
||||
0x000c, 0x000000ff, 0x0040,
|
||||
0x000c, 0xffffffff, 0x0040,
|
||||
0x000d, 0x00000040, 0x00004040,
|
||||
0x2440, 0x07ffffff, 0x03000000,
|
||||
0x2418, 0x0000007f, 0x00000020,
|
||||
|
|
@ -354,11 +347,16 @@ static const u32 oland_golden_registers[] =
|
|||
0x2b04, 0xffffffff, 0x00000000,
|
||||
0x2b03, 0xffffffff, 0x00003210,
|
||||
0x2235, 0x0000001f, 0x00000010,
|
||||
0x0570, 0x000c0fc0, 0x000c0400
|
||||
0x0570, 0x000c0fc0, 0x000c0400,
|
||||
0x052c, 0x0fffffff, 0xffffffff,
|
||||
0x052d, 0x0fffffff, 0x0fffffff,
|
||||
0x052e, 0x0fffffff, 0x0fffffff,
|
||||
0x052f, 0x0fffffff, 0x0fffffff
|
||||
};
|
||||
|
||||
static const u32 oland_golden_rlc_registers[] =
|
||||
{
|
||||
0x263e, 0xffffffff, 0x02010002,
|
||||
0x3109, 0xffffffff, 0x00601005,
|
||||
0x311f, 0xffffffff, 0x10104040,
|
||||
0x3122, 0xffffffff, 0x0100000a,
|
||||
|
|
@ -368,22 +366,27 @@ static const u32 oland_golden_rlc_registers[] =
|
|||
|
||||
static const u32 hainan_golden_registers[] =
|
||||
{
|
||||
0x17bc, 0x00000030, 0x00000011,
|
||||
0x2684, 0x00010000, 0x00018208,
|
||||
0x260c, 0xffffffff, 0x00000000,
|
||||
0x260d, 0xf00fffff, 0x00000400,
|
||||
0x260e, 0x0002021c, 0x00020200,
|
||||
0x4595, 0xff000fff, 0x00000100,
|
||||
0x031e, 0x00000080, 0x00000000,
|
||||
0x3430, 0xff000fff, 0x00000100,
|
||||
0x340c, 0x000300c0, 0x00800040,
|
||||
0x3630, 0xff000fff, 0x00000100,
|
||||
0x360c, 0x000300c0, 0x00800040,
|
||||
0x16ec, 0x000000f0, 0x00000070,
|
||||
0x16f0, 0x00200000, 0x50100000,
|
||||
0x1c0c, 0x31000311, 0x00000011,
|
||||
0x0ab9, 0x00073ffe, 0x000022a2,
|
||||
0x0903, 0x000007ff, 0x00000000,
|
||||
0x2285, 0xf000001f, 0x00000007,
|
||||
0x22c9, 0xffffffff, 0x00ffffff,
|
||||
0x22c4, 0x0000ff0f, 0x00000000,
|
||||
0xa393, 0x07ffffff, 0x4e000000,
|
||||
0xa293, 0x07ffffff, 0x4e000000,
|
||||
0xa0d4, 0x3f3f3fff, 0x00000000,
|
||||
0x000c, 0x000000ff, 0x0040,
|
||||
0x000c, 0xffffffff, 0x0040,
|
||||
0x000d, 0x00000040, 0x00004040,
|
||||
0x2440, 0x03e00000, 0x03600000,
|
||||
0x2418, 0x0000007f, 0x00000020,
|
||||
|
|
@ -392,12 +395,16 @@ static const u32 hainan_golden_registers[] =
|
|||
0x2b04, 0xffffffff, 0x00000000,
|
||||
0x2b03, 0xffffffff, 0x00003210,
|
||||
0x2235, 0x0000001f, 0x00000010,
|
||||
0x0570, 0x000c0fc0, 0x000c0400
|
||||
0x0570, 0x000c0fc0, 0x000c0400,
|
||||
0x052c, 0x0fffffff, 0xffffffff,
|
||||
0x052d, 0x0fffffff, 0x0fffffff,
|
||||
0x052e, 0x0fffffff, 0x0fffffff,
|
||||
0x052f, 0x0fffffff, 0x0fffffff
|
||||
};
|
||||
|
||||
static const u32 hainan_golden_registers2[] =
|
||||
{
|
||||
0x263e, 0xffffffff, 0x02010001
|
||||
0x263e, 0xffffffff, 0x2011003
|
||||
};
|
||||
|
||||
static const u32 tahiti_mgcg_cgcg_init[] =
|
||||
|
|
@ -513,18 +520,18 @@ static const u32 tahiti_mgcg_cgcg_init[] =
|
|||
0x21c2, 0xffffffff, 0x00900100,
|
||||
0x311e, 0xffffffff, 0x00000080,
|
||||
0x3101, 0xffffffff, 0x0020003f,
|
||||
0xc, 0xffffffff, 0x0000001c,
|
||||
0xd, 0x000f0000, 0x000f0000,
|
||||
0x583, 0xffffffff, 0x00000100,
|
||||
0x409, 0xffffffff, 0x00000100,
|
||||
0x40b, 0x00000101, 0x00000000,
|
||||
0x82a, 0xffffffff, 0x00000104,
|
||||
0x993, 0x000c0000, 0x000c0000,
|
||||
0x992, 0x000c0000, 0x000c0000,
|
||||
0x000c, 0xffffffff, 0x0000001c,
|
||||
0x000d, 0x000f0000, 0x000f0000,
|
||||
0x0583, 0xffffffff, 0x00000100,
|
||||
0x0409, 0xffffffff, 0x00000100,
|
||||
0x040b, 0x00000101, 0x00000000,
|
||||
0x082a, 0xffffffff, 0x00000104,
|
||||
0x0993, 0x000c0000, 0x000c0000,
|
||||
0x0992, 0x000c0000, 0x000c0000,
|
||||
0x1579, 0xff000fff, 0x00000100,
|
||||
0x157a, 0x00000001, 0x00000001,
|
||||
0xbd4, 0x00000001, 0x00000001,
|
||||
0xc33, 0xc0000fff, 0x00000104,
|
||||
0x0bd4, 0x00000001, 0x00000001,
|
||||
0x0c33, 0xc0000fff, 0x00000104,
|
||||
0x3079, 0x00000001, 0x00000001,
|
||||
0x3430, 0xfffffff0, 0x00000100,
|
||||
0x3630, 0xfffffff0, 0x00000100
|
||||
|
|
@ -612,16 +619,16 @@ static const u32 pitcairn_mgcg_cgcg_init[] =
|
|||
0x21c2, 0xffffffff, 0x00900100,
|
||||
0x311e, 0xffffffff, 0x00000080,
|
||||
0x3101, 0xffffffff, 0x0020003f,
|
||||
0xc, 0xffffffff, 0x0000001c,
|
||||
0xd, 0x000f0000, 0x000f0000,
|
||||
0x583, 0xffffffff, 0x00000100,
|
||||
0x409, 0xffffffff, 0x00000100,
|
||||
0x40b, 0x00000101, 0x00000000,
|
||||
0x82a, 0xffffffff, 0x00000104,
|
||||
0x000c, 0xffffffff, 0x0000001c,
|
||||
0x000d, 0x000f0000, 0x000f0000,
|
||||
0x0583, 0xffffffff, 0x00000100,
|
||||
0x0409, 0xffffffff, 0x00000100,
|
||||
0x040b, 0x00000101, 0x00000000,
|
||||
0x082a, 0xffffffff, 0x00000104,
|
||||
0x1579, 0xff000fff, 0x00000100,
|
||||
0x157a, 0x00000001, 0x00000001,
|
||||
0xbd4, 0x00000001, 0x00000001,
|
||||
0xc33, 0xc0000fff, 0x00000104,
|
||||
0x0bd4, 0x00000001, 0x00000001,
|
||||
0x0c33, 0xc0000fff, 0x00000104,
|
||||
0x3079, 0x00000001, 0x00000001,
|
||||
0x3430, 0xfffffff0, 0x00000100,
|
||||
0x3630, 0xfffffff0, 0x00000100
|
||||
|
|
@ -709,18 +716,18 @@ static const u32 verde_mgcg_cgcg_init[] =
|
|||
0x21c2, 0xffffffff, 0x00900100,
|
||||
0x311e, 0xffffffff, 0x00000080,
|
||||
0x3101, 0xffffffff, 0x0020003f,
|
||||
0xc, 0xffffffff, 0x0000001c,
|
||||
0xd, 0x000f0000, 0x000f0000,
|
||||
0x583, 0xffffffff, 0x00000100,
|
||||
0x409, 0xffffffff, 0x00000100,
|
||||
0x40b, 0x00000101, 0x00000000,
|
||||
0x82a, 0xffffffff, 0x00000104,
|
||||
0x993, 0x000c0000, 0x000c0000,
|
||||
0x992, 0x000c0000, 0x000c0000,
|
||||
0x000c, 0xffffffff, 0x0000001c,
|
||||
0x000d, 0x000f0000, 0x000f0000,
|
||||
0x0583, 0xffffffff, 0x00000100,
|
||||
0x0409, 0xffffffff, 0x00000100,
|
||||
0x040b, 0x00000101, 0x00000000,
|
||||
0x082a, 0xffffffff, 0x00000104,
|
||||
0x0993, 0x000c0000, 0x000c0000,
|
||||
0x0992, 0x000c0000, 0x000c0000,
|
||||
0x1579, 0xff000fff, 0x00000100,
|
||||
0x157a, 0x00000001, 0x00000001,
|
||||
0xbd4, 0x00000001, 0x00000001,
|
||||
0xc33, 0xc0000fff, 0x00000104,
|
||||
0x0bd4, 0x00000001, 0x00000001,
|
||||
0x0c33, 0xc0000fff, 0x00000104,
|
||||
0x3079, 0x00000001, 0x00000001,
|
||||
0x3430, 0xfffffff0, 0x00000100,
|
||||
0x3630, 0xfffffff0, 0x00000100
|
||||
|
|
@ -788,18 +795,18 @@ static const u32 oland_mgcg_cgcg_init[] =
|
|||
0x21c2, 0xffffffff, 0x00900100,
|
||||
0x311e, 0xffffffff, 0x00000080,
|
||||
0x3101, 0xffffffff, 0x0020003f,
|
||||
0xc, 0xffffffff, 0x0000001c,
|
||||
0xd, 0x000f0000, 0x000f0000,
|
||||
0x583, 0xffffffff, 0x00000100,
|
||||
0x409, 0xffffffff, 0x00000100,
|
||||
0x40b, 0x00000101, 0x00000000,
|
||||
0x82a, 0xffffffff, 0x00000104,
|
||||
0x993, 0x000c0000, 0x000c0000,
|
||||
0x992, 0x000c0000, 0x000c0000,
|
||||
0x000c, 0xffffffff, 0x0000001c,
|
||||
0x000d, 0x000f0000, 0x000f0000,
|
||||
0x0583, 0xffffffff, 0x00000100,
|
||||
0x0409, 0xffffffff, 0x00000100,
|
||||
0x040b, 0x00000101, 0x00000000,
|
||||
0x082a, 0xffffffff, 0x00000104,
|
||||
0x0993, 0x000c0000, 0x000c0000,
|
||||
0x0992, 0x000c0000, 0x000c0000,
|
||||
0x1579, 0xff000fff, 0x00000100,
|
||||
0x157a, 0x00000001, 0x00000001,
|
||||
0xbd4, 0x00000001, 0x00000001,
|
||||
0xc33, 0xc0000fff, 0x00000104,
|
||||
0x0bd4, 0x00000001, 0x00000001,
|
||||
0x0c33, 0xc0000fff, 0x00000104,
|
||||
0x3079, 0x00000001, 0x00000001,
|
||||
0x3430, 0xfffffff0, 0x00000100,
|
||||
0x3630, 0xfffffff0, 0x00000100
|
||||
|
|
@ -867,15 +874,15 @@ static const u32 hainan_mgcg_cgcg_init[] =
|
|||
0x21c2, 0xffffffff, 0x00900100,
|
||||
0x311e, 0xffffffff, 0x00000080,
|
||||
0x3101, 0xffffffff, 0x0020003f,
|
||||
0xc, 0xffffffff, 0x0000001c,
|
||||
0xd, 0x000f0000, 0x000f0000,
|
||||
0x583, 0xffffffff, 0x00000100,
|
||||
0x409, 0xffffffff, 0x00000100,
|
||||
0x82a, 0xffffffff, 0x00000104,
|
||||
0x993, 0x000c0000, 0x000c0000,
|
||||
0x992, 0x000c0000, 0x000c0000,
|
||||
0xbd4, 0x00000001, 0x00000001,
|
||||
0xc33, 0xc0000fff, 0x00000104,
|
||||
0x000c, 0xffffffff, 0x0000001c,
|
||||
0x000d, 0x000f0000, 0x000f0000,
|
||||
0x0583, 0xffffffff, 0x00000100,
|
||||
0x0409, 0xffffffff, 0x00000100,
|
||||
0x082a, 0xffffffff, 0x00000104,
|
||||
0x0993, 0x000c0000, 0x000c0000,
|
||||
0x0992, 0x000c0000, 0x000c0000,
|
||||
0x0bd4, 0x00000001, 0x00000001,
|
||||
0x0c33, 0xc0000fff, 0x00000104,
|
||||
0x3079, 0x00000001, 0x00000001,
|
||||
0x3430, 0xfffffff0, 0x00000100,
|
||||
0x3630, 0xfffffff0, 0x00000100
|
||||
|
|
@ -1179,6 +1186,8 @@ static int si_common_early_init(void *handle)
|
|||
AMD_CG_SUPPORT_HDP_LS |
|
||||
AMD_CG_SUPPORT_HDP_MGCG;
|
||||
adev->pg_flags = 0;
|
||||
adev->external_rev_id = (adev->rev_id == 0) ? 1 :
|
||||
(adev->rev_id == 1) ? 5 : 6;
|
||||
break;
|
||||
case CHIP_PITCAIRN:
|
||||
adev->cg_flags =
|
||||
|
|
@ -1198,6 +1207,7 @@ static int si_common_early_init(void *handle)
|
|||
AMD_CG_SUPPORT_HDP_LS |
|
||||
AMD_CG_SUPPORT_HDP_MGCG;
|
||||
adev->pg_flags = 0;
|
||||
adev->external_rev_id = adev->rev_id + 20;
|
||||
break;
|
||||
|
||||
case CHIP_VERDE:
|
||||
|
|
@ -1219,7 +1229,7 @@ static int si_common_early_init(void *handle)
|
|||
AMD_CG_SUPPORT_HDP_MGCG;
|
||||
adev->pg_flags = 0;
|
||||
//???
|
||||
adev->external_rev_id = adev->rev_id + 0x14;
|
||||
adev->external_rev_id = adev->rev_id + 40;
|
||||
break;
|
||||
case CHIP_OLAND:
|
||||
adev->cg_flags =
|
||||
|
|
@ -1238,6 +1248,7 @@ static int si_common_early_init(void *handle)
|
|||
AMD_CG_SUPPORT_HDP_LS |
|
||||
AMD_CG_SUPPORT_HDP_MGCG;
|
||||
adev->pg_flags = 0;
|
||||
adev->external_rev_id = 60;
|
||||
break;
|
||||
case CHIP_HAINAN:
|
||||
adev->cg_flags =
|
||||
|
|
@ -1255,6 +1266,7 @@ static int si_common_early_init(void *handle)
|
|||
AMD_CG_SUPPORT_HDP_LS |
|
||||
AMD_CG_SUPPORT_HDP_MGCG;
|
||||
adev->pg_flags = 0;
|
||||
adev->external_rev_id = 70;
|
||||
break;
|
||||
|
||||
default:
|
||||
|
|
|
|||
|
|
@ -932,18 +932,64 @@ static int vi_common_early_init(void *handle)
|
|||
adev->external_rev_id = adev->rev_id + 0x3c;
|
||||
break;
|
||||
case CHIP_TONGA:
|
||||
adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG;
|
||||
adev->pg_flags = AMD_PG_SUPPORT_UVD;
|
||||
adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
|
||||
AMD_CG_SUPPORT_GFX_CGCG |
|
||||
AMD_CG_SUPPORT_GFX_CGLS |
|
||||
AMD_CG_SUPPORT_SDMA_MGCG |
|
||||
AMD_CG_SUPPORT_SDMA_LS |
|
||||
AMD_CG_SUPPORT_BIF_LS |
|
||||
AMD_CG_SUPPORT_HDP_MGCG |
|
||||
AMD_CG_SUPPORT_HDP_LS |
|
||||
AMD_CG_SUPPORT_ROM_MGCG |
|
||||
AMD_CG_SUPPORT_MC_MGCG |
|
||||
AMD_CG_SUPPORT_MC_LS |
|
||||
AMD_CG_SUPPORT_DRM_LS |
|
||||
AMD_CG_SUPPORT_UVD_MGCG;
|
||||
adev->pg_flags = 0;
|
||||
adev->external_rev_id = adev->rev_id + 0x14;
|
||||
break;
|
||||
case CHIP_POLARIS11:
|
||||
adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG |
|
||||
adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
|
||||
AMD_CG_SUPPORT_GFX_RLC_LS |
|
||||
AMD_CG_SUPPORT_GFX_CP_LS |
|
||||
AMD_CG_SUPPORT_GFX_CGCG |
|
||||
AMD_CG_SUPPORT_GFX_CGLS |
|
||||
AMD_CG_SUPPORT_GFX_3D_CGCG |
|
||||
AMD_CG_SUPPORT_GFX_3D_CGLS |
|
||||
AMD_CG_SUPPORT_SDMA_MGCG |
|
||||
AMD_CG_SUPPORT_SDMA_LS |
|
||||
AMD_CG_SUPPORT_BIF_MGCG |
|
||||
AMD_CG_SUPPORT_BIF_LS |
|
||||
AMD_CG_SUPPORT_HDP_MGCG |
|
||||
AMD_CG_SUPPORT_HDP_LS |
|
||||
AMD_CG_SUPPORT_ROM_MGCG |
|
||||
AMD_CG_SUPPORT_MC_MGCG |
|
||||
AMD_CG_SUPPORT_MC_LS |
|
||||
AMD_CG_SUPPORT_DRM_LS |
|
||||
AMD_CG_SUPPORT_UVD_MGCG |
|
||||
AMD_CG_SUPPORT_VCE_MGCG;
|
||||
adev->pg_flags = 0;
|
||||
adev->external_rev_id = adev->rev_id + 0x5A;
|
||||
break;
|
||||
case CHIP_POLARIS10:
|
||||
adev->cg_flags = AMD_CG_SUPPORT_UVD_MGCG |
|
||||
adev->cg_flags = AMD_CG_SUPPORT_GFX_MGCG |
|
||||
AMD_CG_SUPPORT_GFX_RLC_LS |
|
||||
AMD_CG_SUPPORT_GFX_CP_LS |
|
||||
AMD_CG_SUPPORT_GFX_CGCG |
|
||||
AMD_CG_SUPPORT_GFX_CGLS |
|
||||
AMD_CG_SUPPORT_GFX_3D_CGCG |
|
||||
AMD_CG_SUPPORT_GFX_3D_CGLS |
|
||||
AMD_CG_SUPPORT_SDMA_MGCG |
|
||||
AMD_CG_SUPPORT_SDMA_LS |
|
||||
AMD_CG_SUPPORT_BIF_MGCG |
|
||||
AMD_CG_SUPPORT_BIF_LS |
|
||||
AMD_CG_SUPPORT_HDP_MGCG |
|
||||
AMD_CG_SUPPORT_HDP_LS |
|
||||
AMD_CG_SUPPORT_ROM_MGCG |
|
||||
AMD_CG_SUPPORT_MC_MGCG |
|
||||
AMD_CG_SUPPORT_MC_LS |
|
||||
AMD_CG_SUPPORT_DRM_LS |
|
||||
AMD_CG_SUPPORT_UVD_MGCG |
|
||||
AMD_CG_SUPPORT_VCE_MGCG;
|
||||
adev->pg_flags = 0;
|
||||
adev->external_rev_id = adev->rev_id + 0x50;
|
||||
|
|
@ -971,6 +1017,7 @@ static int vi_common_early_init(void *handle)
|
|||
adev->pg_flags |= AMD_PG_SUPPORT_GFX_PG |
|
||||
AMD_PG_SUPPORT_GFX_SMG |
|
||||
AMD_PG_SUPPORT_GFX_PIPELINE |
|
||||
AMD_PG_SUPPORT_CP |
|
||||
AMD_PG_SUPPORT_UVD |
|
||||
AMD_PG_SUPPORT_VCE;
|
||||
}
|
||||
|
|
@ -996,6 +1043,7 @@ static int vi_common_early_init(void *handle)
|
|||
adev->pg_flags = AMD_PG_SUPPORT_GFX_PG |
|
||||
AMD_PG_SUPPORT_GFX_SMG |
|
||||
AMD_PG_SUPPORT_GFX_PIPELINE |
|
||||
AMD_PG_SUPPORT_CP |
|
||||
AMD_PG_SUPPORT_UVD |
|
||||
AMD_PG_SUPPORT_VCE;
|
||||
adev->external_rev_id = adev->rev_id + 0x61;
|
||||
|
|
@ -1155,57 +1203,118 @@ static void vi_update_rom_medium_grain_clock_gating(struct amdgpu_device *adev,
|
|||
static int vi_common_set_clockgating_state_by_smu(void *handle,
|
||||
enum amd_clockgating_state state)
|
||||
{
|
||||
uint32_t msg_id, pp_state;
|
||||
uint32_t msg_id, pp_state = 0;
|
||||
uint32_t pp_support_state = 0;
|
||||
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
|
||||
void *pp_handle = adev->powerplay.pp_handle;
|
||||
|
||||
if (state == AMD_CG_STATE_UNGATE)
|
||||
pp_state = 0;
|
||||
else
|
||||
pp_state = PP_STATE_CG | PP_STATE_LS;
|
||||
if (adev->cg_flags & (AMD_CG_SUPPORT_MC_LS | AMD_CG_SUPPORT_MC_MGCG)) {
|
||||
if (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) {
|
||||
pp_support_state = AMD_CG_SUPPORT_MC_LS;
|
||||
pp_state = PP_STATE_LS;
|
||||
}
|
||||
if (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG) {
|
||||
pp_support_state |= AMD_CG_SUPPORT_MC_MGCG;
|
||||
pp_state |= PP_STATE_CG;
|
||||
}
|
||||
if (state == AMD_CG_STATE_UNGATE)
|
||||
pp_state = 0;
|
||||
msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
|
||||
PP_BLOCK_SYS_MC,
|
||||
pp_support_state,
|
||||
pp_state);
|
||||
amd_set_clockgating_by_smu(pp_handle, msg_id);
|
||||
}
|
||||
|
||||
msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
|
||||
PP_BLOCK_SYS_MC,
|
||||
PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
|
||||
pp_state);
|
||||
amd_set_clockgating_by_smu(pp_handle, msg_id);
|
||||
if (adev->cg_flags & (AMD_CG_SUPPORT_SDMA_LS | AMD_CG_SUPPORT_SDMA_MGCG)) {
|
||||
if (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS) {
|
||||
pp_support_state = AMD_CG_SUPPORT_SDMA_LS;
|
||||
pp_state = PP_STATE_LS;
|
||||
}
|
||||
if (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG) {
|
||||
pp_support_state |= AMD_CG_SUPPORT_SDMA_MGCG;
|
||||
pp_state |= PP_STATE_CG;
|
||||
}
|
||||
if (state == AMD_CG_STATE_UNGATE)
|
||||
pp_state = 0;
|
||||
msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
|
||||
PP_BLOCK_SYS_SDMA,
|
||||
pp_support_state,
|
||||
pp_state);
|
||||
amd_set_clockgating_by_smu(pp_handle, msg_id);
|
||||
}
|
||||
|
||||
msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
|
||||
PP_BLOCK_SYS_SDMA,
|
||||
PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
|
||||
pp_state);
|
||||
amd_set_clockgating_by_smu(pp_handle, msg_id);
|
||||
if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_MGCG)) {
|
||||
if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) {
|
||||
pp_support_state = AMD_CG_SUPPORT_HDP_LS;
|
||||
pp_state = PP_STATE_LS;
|
||||
}
|
||||
if (adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG) {
|
||||
pp_support_state |= AMD_CG_SUPPORT_HDP_MGCG;
|
||||
pp_state |= PP_STATE_CG;
|
||||
}
|
||||
if (state == AMD_CG_STATE_UNGATE)
|
||||
pp_state = 0;
|
||||
msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
|
||||
PP_BLOCK_SYS_HDP,
|
||||
pp_support_state,
|
||||
pp_state);
|
||||
amd_set_clockgating_by_smu(pp_handle, msg_id);
|
||||
}
|
||||
|
||||
msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
|
||||
PP_BLOCK_SYS_HDP,
|
||||
PP_STATE_SUPPORT_CG | PP_STATE_SUPPORT_LS,
|
||||
pp_state);
|
||||
amd_set_clockgating_by_smu(pp_handle, msg_id);
|
||||
|
||||
msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
|
||||
PP_BLOCK_SYS_BIF,
|
||||
PP_STATE_SUPPORT_LS,
|
||||
pp_state);
|
||||
amd_set_clockgating_by_smu(pp_handle, msg_id);
|
||||
if (adev->cg_flags & AMD_CG_SUPPORT_BIF_LS) {
|
||||
if (state == AMD_CG_STATE_UNGATE)
|
||||
pp_state = 0;
|
||||
else
|
||||
pp_state = PP_STATE_LS;
|
||||
|
||||
msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
|
||||
PP_BLOCK_SYS_BIF,
|
||||
PP_STATE_SUPPORT_CG,
|
||||
pp_state);
|
||||
amd_set_clockgating_by_smu(pp_handle, msg_id);
|
||||
msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
|
||||
PP_BLOCK_SYS_BIF,
|
||||
PP_STATE_SUPPORT_LS,
|
||||
pp_state);
|
||||
amd_set_clockgating_by_smu(pp_handle, msg_id);
|
||||
}
|
||||
if (adev->cg_flags & AMD_CG_SUPPORT_BIF_MGCG) {
|
||||
if (state == AMD_CG_STATE_UNGATE)
|
||||
pp_state = 0;
|
||||
else
|
||||
pp_state = PP_STATE_CG;
|
||||
|
||||
msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
|
||||
PP_BLOCK_SYS_DRM,
|
||||
PP_STATE_SUPPORT_LS,
|
||||
pp_state);
|
||||
amd_set_clockgating_by_smu(pp_handle, msg_id);
|
||||
msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
|
||||
PP_BLOCK_SYS_BIF,
|
||||
PP_STATE_SUPPORT_CG,
|
||||
pp_state);
|
||||
amd_set_clockgating_by_smu(pp_handle, msg_id);
|
||||
}
|
||||
|
||||
msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
|
||||
PP_BLOCK_SYS_ROM,
|
||||
PP_STATE_SUPPORT_CG,
|
||||
pp_state);
|
||||
amd_set_clockgating_by_smu(pp_handle, msg_id);
|
||||
if (adev->cg_flags & AMD_CG_SUPPORT_DRM_LS) {
|
||||
|
||||
if (state == AMD_CG_STATE_UNGATE)
|
||||
pp_state = 0;
|
||||
else
|
||||
pp_state = PP_STATE_LS;
|
||||
|
||||
msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
|
||||
PP_BLOCK_SYS_DRM,
|
||||
PP_STATE_SUPPORT_LS,
|
||||
pp_state);
|
||||
amd_set_clockgating_by_smu(pp_handle, msg_id);
|
||||
}
|
||||
|
||||
if (adev->cg_flags & AMD_CG_SUPPORT_ROM_MGCG) {
|
||||
|
||||
if (state == AMD_CG_STATE_UNGATE)
|
||||
pp_state = 0;
|
||||
else
|
||||
pp_state = PP_STATE_CG;
|
||||
|
||||
msg_id = PP_CG_MSG_ID(PP_GROUP_SYS,
|
||||
PP_BLOCK_SYS_ROM,
|
||||
PP_STATE_SUPPORT_CG,
|
||||
pp_state);
|
||||
amd_set_clockgating_by_smu(pp_handle, msg_id);
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -126,6 +126,10 @@ enum amd_vce_level {
|
|||
#define AMD_CG_SUPPORT_HDP_LS (1 << 15)
|
||||
#define AMD_CG_SUPPORT_HDP_MGCG (1 << 16)
|
||||
#define AMD_CG_SUPPORT_ROM_MGCG (1 << 17)
|
||||
#define AMD_CG_SUPPORT_DRM_LS (1 << 18)
|
||||
#define AMD_CG_SUPPORT_BIF_MGCG (1 << 19)
|
||||
#define AMD_CG_SUPPORT_GFX_3D_CGCG (1 << 20)
|
||||
#define AMD_CG_SUPPORT_GFX_3D_CGLS (1 << 21)
|
||||
|
||||
/* PG flags */
|
||||
#define AMD_PG_SUPPORT_GFX_PG (1 << 0)
|
||||
|
|
|
|||
Loading…
Reference in New Issue