[SPARC64]: Fill dead cycles on trap entry with real work.
As we save trap state onto the stack, the store buffer fills up mid-way through and we stall for several cycles as the store buffer trickles out to the L2 cache. Meanwhile we can do some privileged register reads and other calculations, essentially for free. Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -98,37 +98,40 @@ etrap_save: save %g2, -STACK_BIAS, %sp
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stxa %g3, [%l4] ASI_DMMU
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sethi %hi(KERNBASE), %l4
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flush %l4
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wr %g0, ASI_AIUS, %asi
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2: wrpr %g0, 0x0, %tl
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mov %g4, %l4
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mov ASI_AIUS, %l7
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2: mov %g4, %l4
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mov %g5, %l5
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mov %g7, %l2
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add %g7, 4, %l2
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wrpr %g0, ETRAP_PSTATE1, %pstate
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stx %g1, [%sp + PTREGS_OFF + PT_V9_G1]
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stx %g2, [%sp + PTREGS_OFF + PT_V9_G2]
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sllx %l7, 24, %l7
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stx %g3, [%sp + PTREGS_OFF + PT_V9_G3]
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rdpr %cwp, %l0
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stx %g4, [%sp + PTREGS_OFF + PT_V9_G4]
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stx %g5, [%sp + PTREGS_OFF + PT_V9_G5]
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stx %g6, [%sp + PTREGS_OFF + PT_V9_G6]
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stx %g7, [%sp + PTREGS_OFF + PT_V9_G7]
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or %l7, %l0, %l7
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sethi %hi(TSTATE_RMO | TSTATE_PEF), %l0
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or %l7, %l0, %l7
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wrpr %l2, %tnpc
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wrpr %l7, (TSTATE_PRIV | TSTATE_IE), %tstate
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stx %i0, [%sp + PTREGS_OFF + PT_V9_I0]
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stx %i1, [%sp + PTREGS_OFF + PT_V9_I1]
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stx %i2, [%sp + PTREGS_OFF + PT_V9_I2]
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stx %i3, [%sp + PTREGS_OFF + PT_V9_I3]
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stx %i4, [%sp + PTREGS_OFF + PT_V9_I4]
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stx %i5, [%sp + PTREGS_OFF + PT_V9_I5]
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stx %i6, [%sp + PTREGS_OFF + PT_V9_I6]
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stx %i7, [%sp + PTREGS_OFF + PT_V9_I7]
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wrpr %g0, ETRAP_PSTATE2, %pstate
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mov %l6, %g6
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stx %i7, [%sp + PTREGS_OFF + PT_V9_I7]
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LOAD_PER_CPU_BASE(%g5, %g6, %g4, %g3, %l1)
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jmpl %l2 + 0x4, %g0
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ldx [%g6 + TI_TASK], %g4
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ldx [%g6 + TI_TASK], %g4
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done
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3: ldub [%l6 + TI_FPDEPTH], %l5
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3: mov ASI_P, %l7
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ldub [%l6 + TI_FPDEPTH], %l5
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add %l6, TI_FPSAVED + 1, %l4
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srl %l5, 1, %l3
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add %l5, 2, %l5
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