clk: meson: gxbb-aoclk: migrate to the new parent description method
This clock controller use the string comparison method to describe parent relation between the clocks, which is not optimized. Migrate to the new way by using .parent_hws where possible (when parent clocks are localy declared in the controller) and use .parent_data otherwise. Remove clk input helper and all bypass clocks (declared in probe function) which are no longer used since we are able to use device-tree clock name directly. Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>alistair/sunxi64-5.4-dsi
Alexandre Mergnat
Jerome Brunet
parent
ba62608110
commit
6e2bfc352e
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@ -11,8 +11,6 @@
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#include "clk-regmap.h"
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#include "clk-dualdiv.h"
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#define IN_PREFIX "ao-in-"
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/* AO Configuration Clock registers offsets */
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#define AO_RTI_PWR_CNTL_REG1 0x0c
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#define AO_RTI_PWR_CNTL_REG0 0x10
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@ -31,7 +29,9 @@ static struct clk_regmap _name##_ao = { \
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.hw.init = &(struct clk_init_data) { \
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.name = #_name "_ao", \
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.ops = &clk_regmap_gate_ops, \
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.parent_names = (const char *[]){ IN_PREFIX "mpeg-clk" }, \
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.parent_data = &(const struct clk_parent_data) { \
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.fw_name = "mpeg-clk", \
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}, \
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.num_parents = 1, \
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.flags = CLK_IGNORE_UNUSED, \
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}, \
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@ -52,7 +52,9 @@ static struct clk_regmap ao_cts_oscin = {
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.hw.init = &(struct clk_init_data){
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.name = "ao_cts_oscin",
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.ops = &clk_regmap_gate_ro_ops,
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.parent_names = (const char *[]){ IN_PREFIX "xtal" },
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.parent_data = &(const struct clk_parent_data) {
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.fw_name = "xtal",
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},
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.num_parents = 1,
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},
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};
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@ -65,7 +67,7 @@ static struct clk_regmap ao_32k_pre = {
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.hw.init = &(struct clk_init_data){
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.name = "ao_32k_pre",
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.ops = &clk_regmap_gate_ops,
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.parent_names = (const char *[]){ "ao_cts_oscin" },
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.parent_hws = (const struct clk_hw *[]) { &ao_cts_oscin.hw },
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.num_parents = 1,
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},
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};
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@ -112,7 +114,7 @@ static struct clk_regmap ao_32k_div = {
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.hw.init = &(struct clk_init_data){
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.name = "ao_32k_div",
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.ops = &meson_clk_dualdiv_ops,
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.parent_names = (const char *[]){ "ao_32k_pre" },
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.parent_hws = (const struct clk_hw *[]) { &ao_32k_pre.hw },
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.num_parents = 1,
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},
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};
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@ -127,8 +129,10 @@ static struct clk_regmap ao_32k_sel = {
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.hw.init = &(struct clk_init_data){
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.name = "ao_32k_sel",
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.ops = &clk_regmap_mux_ops,
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.parent_names = (const char *[]){ "ao_32k_div",
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"ao_32k_pre" },
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.parent_hws = (const struct clk_hw *[]) {
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&ao_32k_div.hw,
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&ao_32k_pre.hw
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},
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.num_parents = 2,
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.flags = CLK_SET_RATE_PARENT,
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},
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@ -142,7 +146,7 @@ static struct clk_regmap ao_32k = {
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.hw.init = &(struct clk_init_data){
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.name = "ao_32k",
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.ops = &clk_regmap_gate_ops,
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.parent_names = (const char *[]){ "ao_32k_sel" },
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.parent_hws = (const struct clk_hw *[]) { &ao_32k_sel.hw },
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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},
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@ -159,10 +163,12 @@ static struct clk_regmap ao_cts_rtc_oscin = {
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.hw.init = &(struct clk_init_data){
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.name = "ao_cts_rtc_oscin",
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.ops = &clk_regmap_mux_ops,
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.parent_names = (const char *[]){ IN_PREFIX "ext-32k-0",
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IN_PREFIX "ext-32k-1",
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IN_PREFIX "ext-32k-2",
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"ao_32k" },
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.parent_data = (const struct clk_parent_data []) {
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{ .fw_name = "ext-32k-0", },
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{ .fw_name = "ext-32k-1", },
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{ .fw_name = "ext-32k-2", },
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{ .hw = &ao_32k.hw },
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},
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.num_parents = 4,
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.flags = CLK_SET_RATE_PARENT,
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},
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@ -178,8 +184,10 @@ static struct clk_regmap ao_clk81 = {
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.hw.init = &(struct clk_init_data){
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.name = "ao_clk81",
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.ops = &clk_regmap_mux_ro_ops,
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.parent_names = (const char *[]){ IN_PREFIX "mpeg-clk",
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"ao_cts_rtc_oscin" },
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.parent_data = (const struct clk_parent_data []) {
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{ .fw_name = "mpeg-clk", },
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{ .hw = &ao_cts_rtc_oscin.hw },
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},
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.num_parents = 2,
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.flags = CLK_SET_RATE_PARENT,
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},
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@ -208,8 +216,10 @@ static struct clk_regmap ao_cts_cec = {
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* Until CCF gets fixed, adding this fake parent that won't
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* ever be registered should work around the problem
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*/
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.parent_names = (const char *[]){ "fixme",
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"ao_cts_rtc_oscin" },
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.parent_data = (const struct clk_parent_data []) {
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{ .name = "fixme", .index = -1, },
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{ .hw = &ao_cts_rtc_oscin.hw },
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},
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.num_parents = 2,
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.flags = CLK_SET_RATE_PARENT,
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},
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@ -261,14 +271,6 @@ static const struct clk_hw_onecell_data gxbb_aoclk_onecell_data = {
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.num = NR_CLKS,
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};
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static const struct meson_aoclk_input gxbb_aoclk_inputs[] = {
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{ .name = "xtal", .required = true, },
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{ .name = "mpeg-clk", .required = true, },
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{. name = "ext-32k-0", .required = false, },
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{. name = "ext-32k-1", .required = false, },
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{. name = "ext-32k-2", .required = false, },
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};
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static const struct meson_aoclk_data gxbb_aoclkc_data = {
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.reset_reg = AO_RTI_GEN_CNTL_REG0,
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.num_reset = ARRAY_SIZE(gxbb_aoclk_reset),
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@ -276,9 +278,6 @@ static const struct meson_aoclk_data gxbb_aoclkc_data = {
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.num_clks = ARRAY_SIZE(gxbb_aoclk),
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.clks = gxbb_aoclk,
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.hw_data = &gxbb_aoclk_onecell_data,
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.inputs = gxbb_aoclk_inputs,
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.num_inputs = ARRAY_SIZE(gxbb_aoclk_inputs),
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.input_prefix = IN_PREFIX,
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};
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static const struct of_device_id gxbb_aoclkc_match_table[] = {
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