[POWERPC] 4xx: Use dcri_clrset() for PCIe indirect dcr read/modify/write access
Use dcri_clrset() for PCIe SDR0 read/modify/write access. Signed-off-by: Valentine Barshak <vbarshak@ru.mvista.com> Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
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@ -646,7 +646,7 @@ static int __init ppc440spe_pciex_core_init(struct device_node *np)
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int time_out = 20;
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/* Set PLL clock receiver to LVPECL */
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mtdcri(SDR0, PESDR0_PLLLCT1, mfdcri(SDR0, PESDR0_PLLLCT1) | 1 << 28);
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dcri_clrset(SDR0, PESDR0_PLLLCT1, 0, 1 << 28);
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/* Shouldn't we do all the calibration stuff etc... here ? */
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if (ppc440spe_pciex_check_reset(np))
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@ -660,8 +660,7 @@ static int __init ppc440spe_pciex_core_init(struct device_node *np)
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}
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/* De-assert reset of PCIe PLL, wait for lock */
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mtdcri(SDR0, PESDR0_PLLLCT1,
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mfdcri(SDR0, PESDR0_PLLLCT1) & ~(1 << 24));
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dcri_clrset(SDR0, PESDR0_PLLLCT1, 1 << 24, 0);
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udelay(3);
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while (time_out) {
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@ -713,9 +712,8 @@ static int ppc440spe_pciex_init_port_hw(struct ppc4xx_pciex_port *port)
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mtdcri(SDR0, port->sdr_base + PESDRn_440SPE_HSSL7SET1,
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0x35000000);
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}
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val = mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET);
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mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
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(val & ~(1 << 24 | 1 << 16)) | 1 << 12);
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dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET,
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(1 << 24) | (1 << 16), 1 << 12);
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return 0;
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}
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@ -1156,8 +1154,7 @@ static int __init ppc4xx_pciex_port_init(struct ppc4xx_pciex_port *port)
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port->link = 0;
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}
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mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
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mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) | 1 << 20);
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dcri_clrset(SDR0, port->sdr_base + PESDRn_RCSSET, 0, 1 << 20);
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msleep(100);
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return 0;
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