drm/i915: Clean up kerneldoc for intel_lrc.c
Fairly minimal, there's still lots of functions without any docs, and which aren't static. But probably we want to first clean this up some more. - Drop the bogus const. Marking argument pointers themselves (instead of what they point at) as const provides roughly 0 value. And it's confusing, since the data the pointer points at _is_ being changed. - Remove kerneldoc for static functions. Keep comments where they seem valuable. - Indent and whitespace fixes. - Blockquote the bit field definitions of the descriptor for correct layouting. Acked-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch> Link: http://patchwork.freedesktop.org/patch/msgid/1468612088-9721-9-git-send-email-daniel.vetter@ffwll.chhifive-unleashed-5.1
Daniel Vetter
parent
3d466cd67e
commit
6e5248b53f
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@ -288,7 +288,6 @@ logical_ring_init_platform_invariants(struct intel_engine_cs *engine)
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/**
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* intel_lr_context_descriptor_update() - calculate & cache the descriptor
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* descriptor for a pinned context
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*
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* @ctx: Context to work on
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* @engine: Engine the descriptor will be used with
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*
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@ -297,12 +296,13 @@ logical_ring_init_platform_invariants(struct intel_engine_cs *engine)
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* expensive to calculate, we'll just do it once and cache the result,
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* which remains valid until the context is unpinned.
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*
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* This is what a descriptor looks like, from LSB to MSB:
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* bits 0-11: flags, GEN8_CTX_* (cached in ctx_desc_template)
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* bits 12-31: LRCA, GTT address of (the HWSP of) this context
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* bits 32-52: ctx ID, a globally unique tag
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* bits 53-54: mbz, reserved for use by hardware
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* bits 55-63: group ID, currently unused and set to 0
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* This is what a descriptor looks like, from LSB to MSB::
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*
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* bits 0-11: flags, GEN8_CTX_* (cached in ctx_desc_template)
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* bits 12-31: LRCA, GTT address of (the HWSP of) this context
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* bits 32-52: ctx ID, a globally unique tag
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* bits 53-54: mbz, reserved for use by hardware
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* bits 55-63: group ID, currently unused and set to 0
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*/
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static void
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intel_lr_context_descriptor_update(struct i915_gem_context *ctx,
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@ -539,10 +539,7 @@ get_context_status(struct intel_engine_cs *engine, unsigned int read_pointer,
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return status;
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}
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/**
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* intel_lrc_irq_handler() - handle Context Switch interrupts
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* @data: tasklet handler passed in unsigned long
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*
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/*
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* Check the unread Context Status Buffers and manage the submission of new
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* contexts to the ELSP accordingly.
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*/
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@ -807,7 +804,7 @@ intel_logical_ring_advance_and_submit(struct drm_i915_gem_request *request)
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}
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/**
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* execlists_submission() - submit a batchbuffer for execution, Execlists style
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* intel_execlists_submission() - submit a batchbuffer for execution, Execlists style
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* @params: execbuffer call parameters.
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* @args: execbuffer call arguments.
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* @vmas: list of vmas.
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@ -1094,7 +1091,7 @@ static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req)
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* code duplication.
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*/
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static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine,
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uint32_t *const batch,
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uint32_t *batch,
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uint32_t index)
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{
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uint32_t l3sqc4_flush = (0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES);
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@ -1155,37 +1152,24 @@ static inline int wa_ctx_end(struct i915_wa_ctx_bb *wa_ctx,
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return 0;
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}
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/**
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* gen8_init_indirectctx_bb() - initialize indirect ctx batch with WA
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/*
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* Typically we only have one indirect_ctx and per_ctx batch buffer which are
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* initialized at the beginning and shared across all contexts but this field
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* helps us to have multiple batches at different offsets and select them based
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* on a criteria. At the moment this batch always start at the beginning of the page
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* and at this point we don't have multiple wa_ctx batch buffers.
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*
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* @engine: only applicable for RCS
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* @wa_ctx: structure representing wa_ctx
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* offset: specifies start of the batch, should be cache-aligned. This is updated
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* with the offset value received as input.
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* size: size of the batch in DWORDS but HW expects in terms of cachelines
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* @batch: page in which WA are loaded
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* @offset: This field specifies the start of the batch, it should be
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* cache-aligned otherwise it is adjusted accordingly.
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* Typically we only have one indirect_ctx and per_ctx batch buffer which are
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* initialized at the beginning and shared across all contexts but this field
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* helps us to have multiple batches at different offsets and select them based
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* on a criteria. At the moment this batch always start at the beginning of the page
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* and at this point we don't have multiple wa_ctx batch buffers.
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* The number of WA applied are not known at the beginning; we use this field
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* to return the no of DWORDS written.
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*
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* The number of WA applied are not known at the beginning; we use this field
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* to return the no of DWORDS written.
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*
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* It is to be noted that this batch does not contain MI_BATCH_BUFFER_END
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* so it adds NOOPs as padding to make it cacheline aligned.
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* MI_BATCH_BUFFER_END will be added to perctx batch and both of them together
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* makes a complete batch buffer.
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*
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* Return: non-zero if we exceed the PAGE_SIZE limit.
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* It is to be noted that this batch does not contain MI_BATCH_BUFFER_END
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* so it adds NOOPs as padding to make it cacheline aligned.
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* MI_BATCH_BUFFER_END will be added to perctx batch and both of them together
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* makes a complete batch buffer.
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*/
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static int gen8_init_indirectctx_bb(struct intel_engine_cs *engine,
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struct i915_wa_ctx_bb *wa_ctx,
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uint32_t *const batch,
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uint32_t *batch,
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uint32_t *offset)
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{
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uint32_t scratch_addr;
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@ -1229,26 +1213,18 @@ static int gen8_init_indirectctx_bb(struct intel_engine_cs *engine,
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return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS);
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}
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/**
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* gen8_init_perctx_bb() - initialize per ctx batch with WA
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/*
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* This batch is started immediately after indirect_ctx batch. Since we ensure
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* that indirect_ctx ends on a cacheline this batch is aligned automatically.
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*
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* @engine: only applicable for RCS
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* @wa_ctx: structure representing wa_ctx
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* offset: specifies start of the batch, should be cache-aligned.
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* size: size of the batch in DWORDS but HW expects in terms of cachelines
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* @batch: page in which WA are loaded
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* @offset: This field specifies the start of this batch.
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* This batch is started immediately after indirect_ctx batch. Since we ensure
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* that indirect_ctx ends on a cacheline this batch is aligned automatically.
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*
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* The number of DWORDS written are returned using this field.
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* The number of DWORDS written are returned using this field.
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*
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* This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding
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* to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant.
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*/
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static int gen8_init_perctx_bb(struct intel_engine_cs *engine,
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struct i915_wa_ctx_bb *wa_ctx,
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uint32_t *const batch,
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uint32_t *batch,
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uint32_t *offset)
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{
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uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
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@ -1263,7 +1239,7 @@ static int gen8_init_perctx_bb(struct intel_engine_cs *engine,
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static int gen9_init_indirectctx_bb(struct intel_engine_cs *engine,
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struct i915_wa_ctx_bb *wa_ctx,
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uint32_t *const batch,
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uint32_t *batch,
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uint32_t *offset)
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{
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int ret;
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@ -1330,7 +1306,7 @@ static int gen9_init_indirectctx_bb(struct intel_engine_cs *engine,
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static int gen9_init_perctx_bb(struct intel_engine_cs *engine,
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struct i915_wa_ctx_bb *wa_ctx,
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uint32_t *const batch,
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uint32_t *batch,
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uint32_t *offset)
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{
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uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS);
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@ -1916,9 +1892,7 @@ static int gen8_init_rcs_context(struct drm_i915_gem_request *req)
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/**
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* intel_logical_ring_cleanup() - deallocate the Engine Command Streamer
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*
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* @engine: Engine Command Streamer.
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*
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*/
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void intel_logical_ring_cleanup(struct intel_engine_cs *engine)
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{
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@ -2365,19 +2339,6 @@ uint32_t intel_lr_context_size(struct intel_engine_cs *engine)
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return ret;
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}
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/**
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* execlists_context_deferred_alloc() - create the LRC specific bits of a context
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* @ctx: LR context to create.
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* @engine: engine to be used with the context.
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*
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* This function can be called more than once, with different engines, if we plan
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* to use the context with them. The context backing objects and the ringbuffers
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* (specially the ringbuffer backing objects) suck a lot of memory up, and that's why
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* the creation is a deferred call: it's better to make sure first that we need to use
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* a given ring with the context.
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*
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* Return: non-zero on error.
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*/
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static int execlists_context_deferred_alloc(struct i915_gem_context *ctx,
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struct intel_engine_cs *engine)
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{
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