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Xtensa fixes for v5.3: 

- add missing isync into cpu_reset to make sure ITLB changes are
   effective.
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Merge tag 'xtensa-20190816' of git://github.com/jcmvbkbc/linux-xtensa

Pull Xtensa fix from Max Filippov:
 "Add missing isync into cpu_reset to make sure ITLB changes are
  effective"

* tag 'xtensa-20190816' of git://github.com/jcmvbkbc/linux-xtensa:
  xtensa: add missing isync to the cpu_reset TLB code
alistair/sunxi64-5.4-dsi
Linus Torvalds 2019-08-16 17:27:55 -07:00
parent b7e7c85dc7 cd8869f4cb
commit 6e625a1a3f
1 changed files with 1 additions and 0 deletions
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arch/xtensa/kernel/setup.c
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@ -511,6 +511,7 @@ void cpu_reset(void)
"add %2, %2, %7\n\t"
"addi %0, %0, -1\n\t"
"bnez %0, 1b\n\t"
"isync\n\t"
/* Jump to identity mapping */
"jx %3\n"
"2:\n\t"