drm/amd/display: Add get_firmware_info_v3_2 for VG12
Signed-off-by: Harry Wentland <harry.wentland@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -70,6 +70,10 @@ static enum bp_result get_firmware_info_v3_1(
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struct bios_parser *bp,
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struct dc_firmware_info *info);
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static enum bp_result get_firmware_info_v3_2(
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struct bios_parser *bp,
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struct dc_firmware_info *info);
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static struct atom_hpd_int_record *get_hpd_record(struct bios_parser *bp,
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struct atom_display_object_path_v2 *object);
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@ -1321,9 +1325,11 @@ static enum bp_result bios_parser_get_firmware_info(
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case 3:
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switch (revision.minor) {
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case 1:
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case 2:
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result = get_firmware_info_v3_1(bp, info);
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break;
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case 2:
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result = get_firmware_info_v3_2(bp, info);
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break;
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default:
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break;
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}
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@ -1383,6 +1389,84 @@ static enum bp_result get_firmware_info_v3_1(
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return BP_RESULT_OK;
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}
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static enum bp_result get_firmware_info_v3_2(
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struct bios_parser *bp,
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struct dc_firmware_info *info)
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{
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struct atom_firmware_info_v3_2 *firmware_info;
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struct atom_display_controller_info_v4_1 *dce_info = NULL;
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struct atom_common_table_header *header;
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struct atom_data_revision revision;
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struct atom_smu_info_v3_2 *smu_info_v3_2 = NULL;
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struct atom_smu_info_v3_3 *smu_info_v3_3 = NULL;
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if (!info)
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return BP_RESULT_BADINPUT;
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firmware_info = GET_IMAGE(struct atom_firmware_info_v3_2,
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DATA_TABLES(firmwareinfo));
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dce_info = GET_IMAGE(struct atom_display_controller_info_v4_1,
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DATA_TABLES(dce_info));
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if (!firmware_info || !dce_info)
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return BP_RESULT_BADBIOSTABLE;
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memset(info, 0, sizeof(*info));
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header = GET_IMAGE(struct atom_common_table_header,
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DATA_TABLES(smu_info));
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get_atom_data_table_revision(header, &revision);
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if (revision.minor == 2) {
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/* Vega12 */
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smu_info_v3_2 = GET_IMAGE(struct atom_smu_info_v3_2,
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DATA_TABLES(smu_info));
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if (!smu_info_v3_2)
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return BP_RESULT_BADBIOSTABLE;
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info->default_engine_clk = smu_info_v3_2->bootup_dcefclk_10khz * 10;
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} else if (revision.minor == 3) {
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/* Vega20 */
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smu_info_v3_3 = GET_IMAGE(struct atom_smu_info_v3_3,
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DATA_TABLES(smu_info));
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if (!smu_info_v3_3)
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return BP_RESULT_BADBIOSTABLE;
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info->default_engine_clk = smu_info_v3_3->bootup_dcefclk_10khz * 10;
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}
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// We need to convert from 10KHz units into KHz units.
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info->default_memory_clk = firmware_info->bootup_mclk_in10khz * 10;
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/* 27MHz for Vega10 & Vega12; 100MHz for Vega20 */
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info->pll_info.crystal_frequency = dce_info->dce_refclk_10khz * 10;
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/* Hardcode frequency if BIOS gives no DCE Ref Clk */
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if (info->pll_info.crystal_frequency == 0) {
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if (revision.minor == 2)
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info->pll_info.crystal_frequency = 27000;
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else if (revision.minor == 3)
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info->pll_info.crystal_frequency = 100000;
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}
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/*dp_phy_ref_clk is not correct for atom_display_controller_info_v4_2, but we don't use it*/
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info->dp_phy_ref_clk = dce_info->dpphy_refclk_10khz * 10;
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info->i2c_engine_ref_clk = dce_info->i2c_engine_refclk_10khz * 10;
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/* Get GPU PLL VCO Clock */
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if (bp->cmd_tbl.get_smu_clock_info != NULL) {
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if (revision.minor == 2)
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info->smu_gpu_pll_output_freq =
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bp->cmd_tbl.get_smu_clock_info(bp, SMU9_SYSPLL0_ID) * 10;
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else if (revision.minor == 3)
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info->smu_gpu_pll_output_freq =
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bp->cmd_tbl.get_smu_clock_info(bp, SMU11_SYSPLL3_0_ID) * 10;
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}
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return BP_RESULT_OK;
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}
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static enum bp_result bios_parser_get_encoder_cap_info(
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struct dc_bios *dcb,
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struct graphics_object_id object_id,
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