redonkable
/
alistair23-linux
1
0
Fork 0
Code Releases Activity

drm/nouveau: Fix a couple of sparse warnings. 

Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
hifive-unleashed-5.1
Francisco Jerez 2010-07-03 18:36:39 +02:00 committed by Ben Skeggs
parent 2ed06b7d97
commit 6e86e04194
9 changed files with 20 additions and 19 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/drm/nouveau/nouveau_acpi.c
View File

@ -42,7 +42,7 @@ static const char nouveau_dsm_muid[] = {
0xB3, 0x4D, 0x7E, 0x5F, 0xEA, 0x12, 0x9F, 0xD4,
};
static int nouveau_dsm(acpi_handle handle, int func, int arg, int *result)
static int nouveau_dsm(acpi_handle handle, int func, int arg, uint32_t *result)
{
struct acpi_buffer output = { ACPI_ALLOCATE_BUFFER, NULL };
struct acpi_object_list input;

7
drivers/gpu/drm/nouveau/nouveau_connector.c
View File

@ -585,7 +585,6 @@ nouveau_connector_get_modes(struct drm_connector *connector)
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nouveau_connector *nv_connector = nouveau_connector(connector);
struct nouveau_encoder *nv_encoder = nv_connector->detected_encoder;
struct drm_display_mode mode;
int ret = 0;
/* destroy the native mode, the attached monitor could have changed.
@ -600,9 +599,9 @@ nouveau_connector_get_modes(struct drm_connector *connector)
else
if (nv_encoder->dcb->type == OUTPUT_LVDS &&
(nv_encoder->dcb->lvdsconf.use_straps_for_mode ||
dev_priv->vbios.fp_no_ddc) &&
nouveau_bios_fp_mode(dev, &mode)) {
nv_connector->native_mode = drm_mode_duplicate(dev, &mode);
dev_priv->vbios.fp_no_ddc) && nouveau_bios_fp_mode(dev, NULL)) {
nv_connector->native_mode = drm_mode_create(dev);
nouveau_bios_fp_mode(dev, nv_connector->native_mode);
}
/* Find the native mode if this is a digital panel, if we didn't

1
drivers/gpu/drm/nouveau/nouveau_drv.c
View File

@ -317,7 +317,6 @@ nouveau_pci_resume(struct pci_dev *pdev)
list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
int ret;
ret = nouveau_bo_pin(nv_crtc->cursor.nvbo, TTM_PL_FLAG_VRAM);
if (!ret)

2
drivers/gpu/drm/nouveau/nouveau_fbcon.c
View File

@ -333,7 +333,7 @@ nouveau_fbcon_output_poll_changed(struct drm_device *dev)
drm_fb_helper_hotplug_event(&dev_priv->nfbdev->helper);
}
int
static int
nouveau_fbcon_destroy(struct drm_device *dev, struct nouveau_fbdev *nfbdev)
{
struct nouveau_framebuffer *nouveau_fb = &nfbdev->nouveau_fb;

2
drivers/gpu/drm/nouveau/nouveau_gem.c
View File

@ -577,7 +577,7 @@ nouveau_gem_ioctl_pushbuf(struct drm_device *dev, void *data,
struct drm_nouveau_gem_pushbuf_bo *bo;
struct nouveau_channel *chan;
struct validate_op op;
struct nouveau_fence *fence = 0;
struct nouveau_fence *fence = NULL;
int i, j, ret = 0, do_reloc = 0;
NOUVEAU_CHECK_INITIALISED_WITH_RETURN;

2
drivers/gpu/drm/nouveau/nouveau_mem.c
View File

@ -371,7 +371,7 @@ nouveau_mem_detect(struct drm_device *dev)
} else {
dev_priv->vram_size = nv_rd32(dev, NV04_FIFO_DATA);
dev_priv->vram_size |= (dev_priv->vram_size & 0xff) << 32;
dev_priv->vram_size &= 0xffffffff00;
dev_priv->vram_size &= 0xffffffff00ll;
if (dev_priv->chipset == 0xaa || dev_priv->chipset == 0xac) {
dev_priv->vram_sys_base = nv_rd32(dev, 0x100e10);
dev_priv->vram_sys_base <<= 12;

11
drivers/gpu/drm/nouveau/nv04_fifo.c
View File

@ -112,6 +112,12 @@ nv04_fifo_channel_id(struct drm_device *dev)
NV03_PFIFO_CACHE1_PUSH1_CHID_MASK;
}
#ifdef __BIG_ENDIAN
#define DMA_FETCH_ENDIANNESS NV_PFIFO_CACHE1_BIG_ENDIAN
#else
#define DMA_FETCH_ENDIANNESS 0
#endif
int
nv04_fifo_create_context(struct nouveau_channel *chan)
{
@ -138,10 +144,7 @@ nv04_fifo_create_context(struct nouveau_channel *chan)
RAMFC_WR(DMA_FETCH, (NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES |
NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES |
NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8 |
#ifdef __BIG_ENDIAN
NV_PFIFO_CACHE1_BIG_ENDIAN |
#endif
0));
DMA_FETCH_ENDIANNESS));
dev_priv->engine.instmem.finish_access(dev);
/* enable the fifo dma operation */

2
drivers/gpu/drm/nouveau/nv04_graph.c
View File

@ -342,7 +342,7 @@ static uint32_t nv04_graph_ctx_regs[] = {
};
struct graph_state {
int nv04[ARRAY_SIZE(nv04_graph_ctx_regs)];
uint32_t nv04[ARRAY_SIZE(nv04_graph_ctx_regs)];
};
struct nouveau_channel *

10
drivers/gpu/drm/nouveau/nv50_graph.c
View File

@ -212,7 +212,7 @@ nv50_graph_create_context(struct nouveau_channel *chan)
struct drm_device *dev = chan->dev;
struct drm_nouveau_private *dev_priv = dev->dev_private;
struct nouveau_gpuobj *ramin = chan->ramin->gpuobj;
struct nouveau_gpuobj *ctx;
struct nouveau_gpuobj *obj;
struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
int hdr, ret;
@ -223,7 +223,7 @@ nv50_graph_create_context(struct nouveau_channel *chan)
NVOBJ_FLAG_ZERO_FREE, &chan->ramin_grctx);
if (ret)
return ret;
ctx = chan->ramin_grctx->gpuobj;
obj = chan->ramin_grctx->gpuobj;
hdr = IS_G80 ? 0x200 : 0x20;
dev_priv->engine.instmem.prepare_access(dev, true);
@ -241,12 +241,12 @@ nv50_graph_create_context(struct nouveau_channel *chan)
struct nouveau_grctx ctx = {};
ctx.dev = chan->dev;
ctx.mode = NOUVEAU_GRCTX_VALS;
ctx.data = chan->ramin_grctx->gpuobj;
ctx.data = obj;
nv50_grctx_init(&ctx);
} else {
nouveau_grctx_vals_load(dev, ctx);
nouveau_grctx_vals_load(dev, obj);
}
nv_wo32(dev, ctx, 0x00000/4, chan->ramin->instance >> 12);
nv_wo32(dev, obj, 0x00000/4, chan->ramin->instance >> 12);
dev_priv->engine.instmem.finish_access(dev);
return 0;