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m68knommu: create and use a common M53xx ColdFire class of CPUs 

The current CONFIG_M532x support definitions are actually common to a larger
set of version 3 ColdFire CPU types. In the future we want to add support for
the 537x family. It is very similar to the 532x internally, and will be able
to use most of the same definitions.

Create a CONFIG_M53xx option that is enabled to support any of the common
532x and 537x CPU types. Convert the current users of CONFIG_M532x to use
CONFIG_M53xx instead.

Signed-off-by: Greg Ungerer <gerg@uclinux.org>
hifive-unleashed-5.1
Greg Ungerer 2012-11-05 12:01:38 +10:00
parent 0d5340f93c
commit 6eac402783
8 changed files with 21 additions and 17 deletions
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4
arch/m68k/Kconfig.cpu
View File

@ -224,9 +224,13 @@ config M5307
help
Motorola ColdFire 5307 processor support.
config M53xx
bool
config M532x
bool "MCF532x"
depends on !MMU
select M53xx
select HAVE_CACHE_CB
help
Freescale (Motorola) ColdFire 532x processor support.

2
arch/m68k/include/asm/dma.h
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@ -39,7 +39,7 @@
#define MAX_M68K_DMA_CHANNELS 4
#elif defined(CONFIG_M5272)
#define MAX_M68K_DMA_CHANNELS 1
#elif defined(CONFIG_M532x)
#elif defined(CONFIG_M53xx)
#define MAX_M68K_DMA_CHANNELS 0
#else
#define MAX_M68K_DMA_CHANNELS 2

4
arch/m68k/include/asm/m53xxacr.h
View File

@ -55,8 +55,8 @@
#define CACHE_SIZE 0x2000 /* 8k of unified cache */
#define ICACHE_SIZE CACHE_SIZE
#define DCACHE_SIZE CACHE_SIZE
#elif defined(CONFIG_M532x)
#define CACHE_SIZE 0x4000 /* 32k of unified cache */
#elif defined(CONFIG_M53xx)
#define CACHE_SIZE 0x4000 /* 16k of unified cache */
#define ICACHE_SIZE CACHE_SIZE
#define DCACHE_SIZE CACHE_SIZE
#endif

10
arch/m68k/include/asm/m532xsim.h → arch/m68k/include/asm/m53xxsim.h
View File

@ -1,15 +1,15 @@
/****************************************************************************/
/*
* m532xsim.h -- ColdFire 5329 registers
* m53xxsim.h -- ColdFire 5329 registers
*/
/****************************************************************************/
#ifndef m532xsim_h
#define m532xsim_h
#ifndef m53xxsim_h
#define m53xxsim_h
/****************************************************************************/
#define CPU_NAME "COLDFIRE(m532x)"
#define CPU_NAME "COLDFIRE(m53xx)"
#define CPU_INSTR_PER_JIFFY 3
#define MCF_BUSCLK (MCF_CLK / 3)
@ -1238,4 +1238,4 @@
#define MCFEPORT_EPFR (0xFC094006)
/********************************************************************/
#endif /* m532xsim_h */
#endif /* m53xxsim_h */

10
arch/m68k/include/asm/mcfgpio.h
View File

@ -104,7 +104,7 @@ static inline void gpio_free(unsigned gpio)
#if defined(CONFIG_M5206) || defined(CONFIG_M5206e) || \
defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
defined(CONFIG_M532x) || defined(CONFIG_M54xx) || \
defined(CONFIG_M53xx) || defined(CONFIG_M54xx) || \
defined(CONFIG_M5441x)
/* These parts have GPIO organized by 8 bit ports */
@ -139,7 +139,7 @@ static inline void gpio_free(unsigned gpio)
#if defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
defined(CONFIG_M532x) || defined(CONFIG_M5441x)
defined(CONFIG_M53xx) || defined(CONFIG_M5441x)
/*
* These parts have an 'Edge' Port module (external interrupt/GPIO) which uses
* read-modify-write to change an output and a GPIO module which has separate
@ -195,7 +195,7 @@ static inline u32 __mcfgpio_ppdr(unsigned gpio)
return MCFSIM2_GPIO1READ;
#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
defined(CONFIG_M532x) || defined(CONFIG_M5441x)
defined(CONFIG_M53xx) || defined(CONFIG_M5441x)
#if !defined(CONFIG_M5441x)
if (gpio < 8)
return MCFEPORT_EPPDR;
@ -237,7 +237,7 @@ static inline u32 __mcfgpio_podr(unsigned gpio)
return MCFSIM2_GPIO1WRITE;
#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
defined(CONFIG_M532x) || defined(CONFIG_M5441x)
defined(CONFIG_M53xx) || defined(CONFIG_M5441x)
#if !defined(CONFIG_M5441x)
if (gpio < 8)
return MCFEPORT_EPDR;
@ -279,7 +279,7 @@ static inline u32 __mcfgpio_pddr(unsigned gpio)
return MCFSIM2_GPIO1ENABLE;
#elif defined(CONFIG_M520x) || defined(CONFIG_M523x) || \
defined(CONFIG_M527x) || defined(CONFIG_M528x) || \
defined(CONFIG_M532x) || defined(CONFIG_M5441x)
defined(CONFIG_M53xx) || defined(CONFIG_M5441x)
#if !defined(CONFIG_M5441x)
if (gpio < 8)
return MCFEPORT_EPDDR;

4
arch/m68k/include/asm/mcfsim.h
View File

@ -36,8 +36,8 @@
#elif defined(CONFIG_M5307)
#include <asm/m5307sim.h>
#include <asm/mcfintc.h>
#elif defined(CONFIG_M532x)
#include <asm/m532xsim.h>
#elif defined(CONFIG_M53xx)
#include <asm/m53xxsim.h>
#elif defined(CONFIG_M5407)
#include <asm/m5407sim.h>
#include <asm/mcfintc.h>

2
arch/m68k/include/asm/mcftimer.h
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@ -19,7 +19,7 @@
#define MCFTIMER_TRR 0x04 /* Timer Reference (r/w) */
#define MCFTIMER_TCR 0x08 /* Timer Capture reg (r/w) */
#define MCFTIMER_TCN 0x0C /* Timer Counter reg (r/w) */
#if defined(CONFIG_M532x) || defined(CONFIG_M5441x)
#if defined(CONFIG_M53xx) || defined(CONFIG_M5441x)
#define MCFTIMER_TER 0x03 /* Timer Event reg (r/w) */
#else
#define MCFTIMER_TER 0x11 /* Timer Event reg (r/w) */

2
arch/m68k/platform/coldfire/timers.c
View File

@ -36,7 +36,7 @@
*/
void coldfire_profile_init(void);
#if defined(CONFIG_M532x) || defined(CONFIG_M5441x)
#if defined(CONFIG_M53xx) || defined(CONFIG_M5441x)
#define __raw_readtrr __raw_readl
#define __raw_writetrr __raw_writel
#else