tg3: Add error reporting to tg3_phydsp_write()
This patch adds error reporting to the tg3_phydsp_write() function and converts a few more locations to use this function over the inlined equivalent. Reviewed-by: Benjamin Li <benli@broadcom.com> Reviewed-by: Michael Chan <mchan@broadcom.com> Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -1572,10 +1572,15 @@ static void tg3_phy_fini(struct tg3 *tp)
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}
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}
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static void tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
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static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
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{
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tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
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tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
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int err;
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err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
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if (!err)
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err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
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return err;
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}
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static void tg3_phy_fet_toggle_apd(struct tg3 *tp, bool enable)
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@ -1872,8 +1877,7 @@ static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
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tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
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/* Block the PHY control access. */
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tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
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tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0800);
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tg3_phydsp_write(tp, 0x8005, 0x0800);
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err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
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if (!err)
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@ -1884,8 +1888,7 @@ static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
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if (err)
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return err;
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tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8005);
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tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0000);
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tg3_phydsp_write(tp, 0x8005, 0x0000);
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tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
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tg3_writephy(tp, 0x16, 0x0000);
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@ -1994,10 +1997,8 @@ static int tg3_phy_reset(struct tg3 *tp)
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out:
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if (tp->tg3_flags2 & TG3_FLG2_PHY_ADC_BUG) {
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tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
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tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
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tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x2aaa);
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tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
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tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0323);
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tg3_phydsp_write(tp, 0x201f, 0x2aaa);
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tg3_phydsp_write(tp, 0x000a, 0x0323);
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tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
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}
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if (tp->tg3_flags2 & TG3_FLG2_PHY_5704_A0_BUG) {
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@ -2006,12 +2007,9 @@ out:
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}
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if (tp->tg3_flags2 & TG3_FLG2_PHY_BER_BUG) {
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tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
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tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
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tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x310b);
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tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
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tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x9506);
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tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x401f);
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tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x14e2);
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tg3_phydsp_write(tp, 0x000a, 0x310b);
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tg3_phydsp_write(tp, 0x201f, 0x9506);
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tg3_phydsp_write(tp, 0x401f, 0x14e2);
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tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0400);
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} else if (tp->tg3_flags2 & TG3_FLG2_PHY_JITTER_BUG) {
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tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x0c00);
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@ -2979,20 +2977,11 @@ static int tg3_init_5401phy_dsp(struct tg3 *tp)
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/* Set Extended packet length bit */
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err = tg3_writephy(tp, MII_TG3_AUX_CTRL, 0x4c20);
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err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0012);
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err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1804);
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err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x0013);
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err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x1204);
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err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
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err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0132);
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err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8006);
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err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0232);
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err |= tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x201f);
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err |= tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x0a20);
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err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
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err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
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err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
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err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
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err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
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udelay(40);
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