mt76x0: correct RF access via RF_CSR register.
PCIe version don't use MCU for RF registers access. We need to correct RF CSR method to support up to 127 RF registers. Signed-off-by: Stanislaw Gruszka <sgruszka@redhat.com> Signed-off-by: Felix Fietkau <nbd@nbd.name>
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@ -37,7 +37,7 @@ mt76x0_rf_csr_wr(struct mt76x02_dev *dev, u32 offset, u8 value)
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bank = MT_RF_BANK(offset);
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reg = MT_RF_REG(offset);
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if (WARN_ON_ONCE(reg > 64) || WARN_ON_ONCE(bank) > 8)
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if (WARN_ON_ONCE(reg > 127) || WARN_ON_ONCE(bank) > 8)
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return -EINVAL;
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mutex_lock(&dev->phy_mutex);
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@ -76,7 +76,7 @@ static int mt76x0_rf_csr_rr(struct mt76x02_dev *dev, u32 offset)
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bank = MT_RF_BANK(offset);
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reg = MT_RF_REG(offset);
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if (WARN_ON_ONCE(reg > 64) || WARN_ON_ONCE(bank) > 8)
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if (WARN_ON_ONCE(reg > 127) || WARN_ON_ONCE(bank) > 8)
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return -EINVAL;
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mutex_lock(&dev->phy_mutex);
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@ -119,7 +119,6 @@ rf_wr(struct mt76x02_dev *dev, u32 offset, u8 val)
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return mt76_wr_rp(dev, MT_MCU_MEMMAP_RF, &pair, 1);
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} else {
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WARN_ON_ONCE(1);
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return mt76x0_rf_csr_wr(dev, offset, val);
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}
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}
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@ -138,7 +137,6 @@ rf_rr(struct mt76x02_dev *dev, u32 offset)
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ret = mt76_rd_rp(dev, MT_MCU_MEMMAP_RF, &pair, 1);
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val = pair.value;
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} else {
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WARN_ON_ONCE(1);
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ret = val = mt76x0_rf_csr_rr(dev, offset);
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}
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@ -205,8 +205,8 @@
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#define MT_TXQ_STA 0x0434
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#define MT_RF_CSR_CFG 0x0500
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#define MT_RF_CSR_CFG_DATA GENMASK(7, 0)
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#define MT_RF_CSR_CFG_REG_ID GENMASK(13, 8)
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#define MT_RF_CSR_CFG_REG_BANK GENMASK(17, 14)
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#define MT_RF_CSR_CFG_REG_ID GENMASK(14, 8)
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#define MT_RF_CSR_CFG_REG_BANK GENMASK(17, 15)
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#define MT_RF_CSR_CFG_WR BIT(30)
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#define MT_RF_CSR_CFG_KICK BIT(31)
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