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dt-bindings: mmc: add description of PHY delays for sdhci-cadence 

DTS properties are used instead of fixed data
because PHY settings can be different for different chips/boards.
Add description of new DLL PHY delays.

Signed-off-by: Piotr Sroka <piotrs@cadence.com>
Reviewed-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
hifive-unleashed-5.1
Piotr Sroka 2017-03-21 14:33:01 +00:00 committed by Ulf Hansson
parent a0f8243229
commit 6f4b091902
1 changed files with 48 additions and 0 deletions
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48
Documentation/devicetree/bindings/mmc/sdhci-cadence.txt
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@ -19,6 +19,53 @@ if supported. See mmc.txt for details.
- mmc-hs400-1_8v
- mmc-hs400-1_2v
Some PHY delays can be configured by following properties.
PHY DLL input delays:
They are used to delay the data valid window, and align the window
to sampling clock. The delay starts from 5ns (for delay parameter equal to 0)
and it is increased by 2.5ns in each step.
- cdns,phy-input-delay-sd-highspeed:
Value of the delay in the input path for SD high-speed timing
Valid range = [0:0x1F].
- cdns,phy-input-delay-legacy:
Value of the delay in the input path for legacy timing
Valid range = [0:0x1F].
- cdns,phy-input-delay-sd-uhs-sdr12:
Value of the delay in the input path for SD UHS SDR12 timing
Valid range = [0:0x1F].
- cdns,phy-input-delay-sd-uhs-sdr25:
Value of the delay in the input path for SD UHS SDR25 timing
Valid range = [0:0x1F].
- cdns,phy-input-delay-sd-uhs-sdr50:
Value of the delay in the input path for SD UHS SDR50 timing
Valid range = [0:0x1F].
- cdns,phy-input-delay-sd-uhs-ddr50:
Value of the delay in the input path for SD UHS DDR50 timing
Valid range = [0:0x1F].
- cdns,phy-input-delay-mmc-highspeed:
Value of the delay in the input path for MMC high-speed timing
Valid range = [0:0x1F].
- cdns,phy-input-delay-mmc-ddr:
Value of the delay in the input path for eMMC high-speed DDR timing
Valid range = [0:0x1F].
PHY DLL clock delays:
Each delay property represents the fraction of the clock period.
The approximate delay value will be
(<delay property value>/128)*sdmclk_clock_period.
- cdns,phy-dll-delay-sdclk:
Value of the delay introduced on the sdclk output
for all modes except HS200, HS400 and HS400_ES.
Valid range = [0:0x7F].
- cdns,phy-dll-delay-sdclk-hsmmc:
Value of the delay introduced on the sdclk output
for HS200, HS400 and HS400_ES speed modes.
Valid range = [0:0x7F].
- cdns,phy-dll-delay-strobe:
Value of the delay introduced on the dat_strobe input
used in HS400 / HS400_ES speed modes.
Valid range = [0:0x7F].
Example:
emmc: sdhci@5a000000 {
compatible = "socionext,uniphier-sd4hc", "cdns,sd4hc";
@ -29,4 +76,5 @@ Example:
mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
cdns,phy-dll-delay-sdclk = <0>;
};