MLK-23924: dts: arm64: freescale: imx8mm audio board
iMX8MM LPDDR4 SOM on Audio Board 2.0 enable base support SPDIF, ADC and dual DAC Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com> Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>5.4-rM2-2.2.x-imx-squashed
parent
66a3ff6507
commit
6f6ce7b7ad
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@ -55,6 +55,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb imx8mm-evk-rpmsg.dtb imx8mm-evk-rm67191
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imx8mm-evk-usd-wifi.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk-ak4497.dtb imx8mm-evk-ak5558.dtb imx8mm-evk-audio-tdm.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk-8mic-revE.dtb imx8mm-evk-8mic-swpdm.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mm-ab2.dtb
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dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb imx8mn-evk-rm67191.dtb imx8mn-ddr4-evk.dtb imx8mn-ddr4-evk-ak5558.dtb \
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imx8mn-ddr4-evk-rm67191.dtb imx8mn-ddr4-evk-rpmsg.dtb imx8mn-ddr4-evk-usd-wifi.dtb \
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imx8mn-evk-ak5558.dtb imx8mn-evk-rpmsg.dtb
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@ -0,0 +1,864 @@
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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2020 NXP
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*/
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/dts-v1/;
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#include <dt-bindings/usb/pd.h>
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#include "imx8mm.dtsi"
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/ {
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model = "FSL i.MX8MM Audio board 2.0";
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compatible = "fsl,imx8mm-ab2", "fsl,imx8mm";
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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rpmsg_reserved: rpmsg@0xb8000000 {
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no-map;
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reg = <0 0xb8000000 0 0x400000>;
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};
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};
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chosen {
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stdout-path = &uart2;
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};
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leds {
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compatible = "gpio-leds";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_gpio_led>;
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status {
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label = "status";
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gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>;
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default-state = "on";
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};
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panel {
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label = "panel";
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gpios = <&pca6408_2 0 GPIO_ACTIVE_LOW>;
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default-state = "on";
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};
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};
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modem_reset: modem-reset {
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compatible = "gpio-reset";
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reset-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
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reset-delay-us = <2000>;
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reset-post-delay-ms = <40>;
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#reset-cells = <0>;
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};
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reg_sd1_vmmc: sd1_regulator {
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compatible = "regulator-fixed";
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regulator-name = "WLAN_EN";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio2 10 GPIO_ACTIVE_HIGH>;
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off-on-delay-us = <20000>;
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startup-delay-us = <100>;
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enable-active-high;
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};
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reg_usdhc2_vmmc: regulator-usdhc2 {
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compatible = "regulator-fixed";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
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regulator-name = "VSD_3V3";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>;
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off-on-delay-us = <20000>;
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enable-active-high;
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};
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reg_ab2_ana_pwr: regulator-ab2-ana-pwr {
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compatible = "regulator-fixed";
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regulator-name = "ab2_ana_pwr";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ab2_ana_pwr>;
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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regulator-always-on;
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};
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reg_ab2_vdd_pwr_5v0: regulator-ab2-vdd-pwr-5v0 {
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compatible = "regulator-fixed";
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regulator-name = "ab2_vdd_pwr_5v0";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_ab2_vdd_pwr_5v0>;
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regulator-min-microvolt = <5000000>;
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regulator-max-microvolt = <5000000>;
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gpio = <&gpio1 7 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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regulator-always-on;
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};
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bt_sco_codec: bt_sco_codec {
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#sound-dai-cells = <0>;
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compatible = "linux,bt-sco";
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};
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sound-bt-sco {
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compatible = "simple-audio-card";
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simple-audio-card,name = "bt-sco-audio";
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simple-audio-card,format = "i2s";
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simple-audio-card,bitclock-inversion;
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simple-audio-card,frame-master = <&btcpu>;
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simple-audio-card,bitclock-master = <&btcpu>;
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btcpu: simple-audio-card,cpu {
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sound-dai = <&sai2>;
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dai-tdm-slot-num = <2>;
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dai-tdm-slot-width = <16>;
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};
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simple-audio-card,codec {
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sound-dai = <&bt_sco_codec>;
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};
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};
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sound-ak4458 {
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compatible = "fsl,imx-audio-ak4458";
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model = "ak4458-audio";
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audio-cpu = <&sai1>;
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audio-codec = <&ak4458_1>, <&ak4458_2>;
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ak4458,pdn-gpio = <&pca6416 4 GPIO_ACTIVE_HIGH>;
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};
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sound-ak5552 {
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compatible = "fsl,imx-audio-ak5558";
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model = "ak5552-audio";
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audio-cpu = <&sai3>;
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audio-codec = <&ak5552>;
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};
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sound-spdif {
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compatible = "fsl,imx-audio-spdif";
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model = "imx-spdif";
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spdif-controller = <&spdif1>;
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spdif-out;
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spdif-in;
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};
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};
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&A53_0 {
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cpu-supply = <&buck2_reg>;
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};
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&fec1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec1>;
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phy-mode = "rgmii-id";
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phy-handle = <ðphy0>;
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phy-reset-gpios = <&gpio1 5 GPIO_ACTIVE_LOW>;
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phy-reset-post-delay = <150>;
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phy-reset-duration = <10>;
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fsl,magic-packet;
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status = "okay";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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ethphy0: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <1>;
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eee-broken-1000t;
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};
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};
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};
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&sai1 {
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pinctrl-names = "default", "dsd";
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pinctrl-0 = <&pinctrl_sai1>;
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pinctrl-1 = <&pinctrl_sai1_dsd>;
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assigned-clocks = <&clk IMX8MM_CLK_SAI1>;
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assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
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assigned-clock-rates = <49152000>;
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clocks = <&clk IMX8MM_CLK_SAI1_IPG>, <&clk IMX8MM_CLK_DUMMY>,
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<&clk IMX8MM_CLK_SAI1_ROOT>, <&clk IMX8MM_CLK_DUMMY>,
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<&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_AUDIO_PLL1_OUT>,
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<&clk IMX8MM_AUDIO_PLL2_OUT>;
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clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k";
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fsl,sai-multi-lane;
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fsl,dataline,dsd = <0 0xff 0xff 2 0xff 0x11>;
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dmas = <&sdma2 0 25 0>, <&sdma2 1 25 0>;
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status = "okay";
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};
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&sai2 {
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#sound-dai-cells = <0>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sai2>;
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assigned-clocks = <&clk IMX8MM_CLK_SAI2>;
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assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
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assigned-clock-rates = <24576000>;
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status = "okay";
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};
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&sai3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sai3>;
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assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
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assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
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assigned-clock-rates = <24576000>;
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status = "okay";
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};
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&spdif1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_spdif1>;
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assigned-clocks = <&clk IMX8MM_CLK_SPDIF1>;
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assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
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assigned-clock-rates = <24576000>;
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clocks = <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_24M>,
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<&clk IMX8MM_CLK_SPDIF1>, <&clk IMX8MM_CLK_DUMMY>,
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<&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>,
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<&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_DUMMY>,
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<&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>,
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<&clk IMX8MM_AUDIO_PLL1_OUT>, <&clk IMX8MM_AUDIO_PLL2_OUT>;
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clock-names = "core", "rxtx0", "rxtx1", "rxtx2", "rxtx3",
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"rxtx4", "rxtx5", "rxtx6", "rxtx7", "spba", "pll8k", "pll11k";
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status = "okay";
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};
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&snvs_pwrkey {
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status = "okay";
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};
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&uart1 { /* BT */
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart1>;
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assigned-clocks = <&clk IMX8MM_CLK_UART1>;
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assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
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fsl,uart-has-rtscts;
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resets = <&modem_reset>;
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status = "okay";
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};
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&uart2 { /* console */
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart2>;
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status = "okay";
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};
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&uart3 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_uart3>;
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assigned-clocks = <&clk IMX8MM_CLK_UART3>;
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assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
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fsl,uart-has-rtscts;
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status = "okay";
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};
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&usdhc1 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc1_gpio>;
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pinctrl-1 = <&pinctrl_usdhc1_100mhz>, <&pinctrl_usdhc1_gpio>;
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pinctrl-2 = <&pinctrl_usdhc1_200mhz>, <&pinctrl_usdhc1_gpio>;
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bus-width = <4>;
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vmmc-supply = <®_sd1_vmmc>;
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pm-ignore-notify;
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keep-power-in-suspend;
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non-removable;
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status = "okay";
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};
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&usdhc2 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
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pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
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pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
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cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
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bus-width = <4>;
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vmmc-supply = <®_usdhc2_vmmc>;
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status = "okay";
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};
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&usdhc3 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc3>;
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pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
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pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
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bus-width = <8>;
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non-removable;
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status = "okay";
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};
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&wdog1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_wdog>;
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fsl,ext-reset-output;
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status = "okay";
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};
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&flexspi {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_flexspi0>;
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status = "okay";
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flash0: mt25qu256aba@0 {
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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spi-max-frequency = <80000000>;
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spi-tx-bus-width = <4>;
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spi-rx-bus-width = <4>;
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};
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};
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&i2c1 {
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clock-frequency = <400000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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status = "okay";
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pmic@4b {
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compatible = "rohm,bd71847";
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reg = <0x4b>;
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pinctrl-0 = <&pinctrl_pmic>;
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interrupt-parent = <&gpio1>;
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interrupts = <3 GPIO_ACTIVE_LOW>;
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rohm,reset-snvs-powered;
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regulators {
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buck1_reg: BUCK1 {
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regulator-name = "BUCK1";
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regulator-min-microvolt = <700000>;
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regulator-max-microvolt = <1300000>;
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regulator-boot-on;
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regulator-always-on;
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regulator-ramp-delay = <1250>;
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};
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buck2_reg: BUCK2 {
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regulator-name = "BUCK2";
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regulator-min-microvolt = <700000>;
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regulator-max-microvolt = <1300000>;
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regulator-boot-on;
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regulator-always-on;
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regulator-ramp-delay = <1250>;
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rohm,dvs-run-voltage = <1000000>;
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rohm,dvs-idle-voltage = <900000>;
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};
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buck3_reg: BUCK3 {
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// BUCK5 in datasheet
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regulator-name = "BUCK3";
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regulator-min-microvolt = <700000>;
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regulator-max-microvolt = <1350000>;
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regulator-boot-on;
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regulator-always-on;
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};
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buck4_reg: BUCK4 {
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// BUCK6 in datasheet
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regulator-name = "BUCK4";
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regulator-min-microvolt = <3000000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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buck5_reg: BUCK5 {
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// BUCK7 in datasheet
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regulator-name = "BUCK5";
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regulator-min-microvolt = <1605000>;
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regulator-max-microvolt = <1995000>;
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regulator-boot-on;
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regulator-always-on;
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};
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buck6_reg: BUCK6 {
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// BUCK8 in datasheet
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regulator-name = "BUCK6";
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <1400000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo1_reg: LDO1 {
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regulator-name = "LDO1";
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regulator-min-microvolt = <1600000>;
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regulator-max-microvolt = <1900000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo2_reg: LDO2 {
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regulator-name = "LDO2";
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regulator-min-microvolt = <800000>;
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regulator-max-microvolt = <900000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo3_reg: LDO3 {
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regulator-name = "LDO3";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo4_reg: LDO4 {
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regulator-name = "LDO4";
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regulator-min-microvolt = <900000>;
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regulator-max-microvolt = <1800000>;
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regulator-boot-on;
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regulator-always-on;
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};
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ldo6_reg: LDO6 {
|
||||
regulator-name = "LDO6";
|
||||
regulator-min-microvolt = <900000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-boot-on;
|
||||
regulator-always-on;
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&i2c2 {
|
||||
clock-frequency = <400000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2>;
|
||||
status = "okay";
|
||||
|
||||
adv_bridge: adv7535@3d {
|
||||
compatible = "adi,adv7533";
|
||||
reg = <0x3d>;
|
||||
adi,addr-cec = <0x3b>;
|
||||
adi,dsi-lanes = <4>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c2_synaptics_dsx_io>;
|
||||
interrupt-parent = <&gpio1>;
|
||||
interrupts = <9 IRQ_TYPE_LEVEL_LOW>;
|
||||
status = "okay";
|
||||
|
||||
port {
|
||||
adv7535_from_dsim: endpoint {
|
||||
remote-endpoint = <&dsim_to_adv7535>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pca6408_2: gpio@20 {
|
||||
compatible = "ti,tca6408";
|
||||
reg = <0x20>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
vcc-supply = <&buck4_reg>;
|
||||
};
|
||||
|
||||
pca6416_2: gpio@21 {
|
||||
compatible = "ti,tca6416";
|
||||
reg = <0x21>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
vcc-supply = <&buck5_reg>;
|
||||
};
|
||||
};
|
||||
|
||||
&i2c3 {
|
||||
clock-frequency = <100000>;
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_i2c3>;
|
||||
status = "okay";
|
||||
|
||||
pca6416: gpio@20 {
|
||||
compatible = "ti,tca6416";
|
||||
reg = <0x20>;
|
||||
gpio-controller;
|
||||
#gpio-cells = <2>;
|
||||
vcc-supply = <&buck5_reg>;
|
||||
};
|
||||
|
||||
ak4458_1: ak4458@10 {
|
||||
compatible = "asahi-kasei,ak4458";
|
||||
reg = <0x10>;
|
||||
AVDD-supply = <®_ab2_ana_pwr>;
|
||||
DVDD-supply = <®_ab2_vdd_pwr_5v0>;
|
||||
};
|
||||
|
||||
ak4458_2: ak4458@11 {
|
||||
compatible = "asahi-kasei,ak4458";
|
||||
reg = <0x11>;
|
||||
AVDD-supply = <®_ab2_ana_pwr>;
|
||||
DVDD-supply = <®_ab2_vdd_pwr_5v0>;
|
||||
};
|
||||
|
||||
ak4458_3: ak4458@12 {
|
||||
compatible = "asahi-kasei,ak4458";
|
||||
reg = <0x12>;
|
||||
AVDD-supply = <®_ab2_ana_pwr>;
|
||||
DVDD-supply = <®_ab2_vdd_pwr_5v0>;
|
||||
};
|
||||
|
||||
ak5552: ak5552@13 {
|
||||
compatible = "asahi-kasei,ak5552";
|
||||
reg = <0x13>;
|
||||
reset-gpios = <&pca6416 2 GPIO_ACTIVE_HIGH>;
|
||||
AVDD-supply = <®_ab2_ana_pwr>;
|
||||
DVDD-supply = <®_ab2_vdd_pwr_5v0>;
|
||||
};
|
||||
};
|
||||
|
||||
&iomuxc {
|
||||
pinctrl-names = "default";
|
||||
|
||||
pinctrl_fec1: fec1grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_ENET_MDC_ENET1_MDC 0x3
|
||||
MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO 0x3
|
||||
MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f
|
||||
MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f
|
||||
MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f
|
||||
MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f
|
||||
MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91
|
||||
MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91
|
||||
MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91
|
||||
MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91
|
||||
MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f
|
||||
MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91
|
||||
MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91
|
||||
MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f
|
||||
MX8MM_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_flexspi0: flexspi0grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x1c2
|
||||
MX8MM_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82
|
||||
MX8MM_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82
|
||||
MX8MM_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82
|
||||
MX8MM_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82
|
||||
MX8MM_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_gpio_led: gpioledgrp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c1: i2c1grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3
|
||||
MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2: i2c2grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3
|
||||
MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c3: i2c3grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3
|
||||
MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_mipi_dsi_en: mipi_dsi_en {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x16
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_i2c2_synaptics_dsx_io: synaptics_dsx_iogrp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 /* Touch interrupt */
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_pmic: pmicirq {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x41
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ab2_ana_pwr: ab2anapwrgrp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0x41
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_ab2_vdd_pwr_5v0: ab2vddpwr5v0grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x41
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmc {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_sai1: sai1grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6
|
||||
MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6
|
||||
MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0xd6
|
||||
MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6
|
||||
MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6
|
||||
MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6
|
||||
MX8MM_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6
|
||||
MX8MM_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6
|
||||
MX8MM_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6
|
||||
MX8MM_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6
|
||||
MX8MM_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6
|
||||
MX8MM_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_sai1_dsd: sai1grp_dsd {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6
|
||||
MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6
|
||||
MX8MM_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0xd6
|
||||
MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6
|
||||
MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6
|
||||
MX8MM_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6
|
||||
MX8MM_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6
|
||||
MX8MM_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6
|
||||
MX8MM_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6
|
||||
MX8MM_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6
|
||||
MX8MM_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6
|
||||
MX8MM_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_sai2: sai2grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6
|
||||
MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6
|
||||
MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6
|
||||
MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0 0xd6
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_sai3: sai3grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC 0xd6
|
||||
MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK 0xd6
|
||||
MX8MM_IOMUXC_SAI3_MCLK_SAI3_MCLK 0xd6
|
||||
MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0 0xd6
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_spdif1: spdif1grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6
|
||||
MX8MM_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart1: uart1grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140
|
||||
MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140
|
||||
MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B 0x140
|
||||
MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B 0x140
|
||||
MX8MM_IOMUXC_SD1_DATA4_GPIO2_IO6 0x19
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart2: uart2grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140
|
||||
MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_uart3: uart3grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX 0x140
|
||||
MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX 0x140
|
||||
MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x140
|
||||
MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x140
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1_gpio: usdhc1grpgpio {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10 0x41
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1: usdhc1grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x190
|
||||
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d0
|
||||
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d0
|
||||
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d0
|
||||
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d0
|
||||
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x194
|
||||
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d4
|
||||
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d4
|
||||
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d4
|
||||
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d4
|
||||
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d4
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x196
|
||||
MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0x1d6
|
||||
MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0x1d6
|
||||
MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0x1d6
|
||||
MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0x1d6
|
||||
MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0x1d6
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_gpio: usdhc2grpgpio {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x1c4
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2: usdhc2grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x190
|
||||
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d0
|
||||
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d0
|
||||
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d0
|
||||
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d0
|
||||
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d0
|
||||
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194
|
||||
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4
|
||||
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4
|
||||
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4
|
||||
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4
|
||||
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4
|
||||
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196
|
||||
MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6
|
||||
MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6
|
||||
MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6
|
||||
MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6
|
||||
MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6
|
||||
MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3: usdhc3grp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x190
|
||||
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d0
|
||||
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d0
|
||||
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d0
|
||||
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d0
|
||||
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d0
|
||||
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d0
|
||||
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d0
|
||||
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d0
|
||||
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d0
|
||||
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x190
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x194
|
||||
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d4
|
||||
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d4
|
||||
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d4
|
||||
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d4
|
||||
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d4
|
||||
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d4
|
||||
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d4
|
||||
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d4
|
||||
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d4
|
||||
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x194
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK 0x196
|
||||
MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD 0x1d6
|
||||
MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0 0x1d6
|
||||
MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1 0x1d6
|
||||
MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2 0x1d6
|
||||
MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3 0x1d6
|
||||
MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4 0x1d6
|
||||
MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5 0x1d6
|
||||
MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6 0x1d6
|
||||
MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7 0x1d6
|
||||
MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 0x196
|
||||
>;
|
||||
};
|
||||
|
||||
pinctrl_wdog: wdoggrp {
|
||||
fsl,pins = <
|
||||
MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&lcdif {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&mipi_dsi {
|
||||
status = "okay";
|
||||
|
||||
port@1 {
|
||||
dsim_to_adv7535: endpoint {
|
||||
remote-endpoint = <&adv7535_from_dsim>;
|
||||
attach-bridge;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&vpu_g1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vpu_g2 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&vpu_h1 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&gpu {
|
||||
status = "okay";
|
||||
};
|
Loading…
Reference in New Issue