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Documentation: clk: Fix a trivial typo in audss

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Fixes a trivial typo.

Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
This commit is contained in:
Sachin Kamat 2013-07-12 08:53:43 +05:30 committed by Mike Turquette
parent d2127ac451
commit 6f9a4894c4
1 changed files with 1 additions and 1 deletions
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Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
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@ -2,7 +2,7 @@
The Samsung Audio Subsystem clock controller generates and supplies clocks
to Audio Subsystem block available in the S5PV210 and Exynos SoCs. The clock
binding described here is applicable to all SoC's in Exynos family.
binding described here is applicable to all SoCs in Exynos family.
Required Properties: