arm64 arch timer workaround series, including the base patches
that will also go via the arm64 tree. -----BEGIN PGP SIGNATURE----- iQJJBAABCAAzFiEEn9UcU+C1Yxj9lZw9I9DQutE9ekMFAljnmH0VHG1hcmMuenlu Z2llckBhcm0uY29tAAoJECPQ0LrRPXpDkdMP/jMT8ICpKc8G/PD7ru/3dOV9BcFh XLB5dzg1sEkF2NtN6Bcgkl0sMLbr9uaGD2oK55Nf5ryooSCbDkNjOFSwPj5M+XVc bqOYnt0oOYv7LYoGwO9rqIr1z+z3+6ZHDafLCqNcyTsO1qHKNLFEE4DmsxuqrN7v tjyH6v42WBsXvCqAxAhsz/vFWPeKEM5Z4NdwoDrSb8syQZPBG/xUin6tOFZBM9fY tVyiVkpGKyfyfAlPBzoFtvA21Ur2m3wx9I/i8X5NDbAQwjPaHh8RVtRjO5M+5O7O jG/T+ixd/EBlIs89AgMKnv0Tycrm4zVzRMcam+5u89z/M+6V2ifobTTCgmzNDxGh iwAfOboJ2rEZxFHJfKvuj4bVnzO/PnOAx8R5DBn+1eAn1Ox4N1weXXpFaUV9HZtN 4p61eDk5xhkRPoSAUnZz72YpsN/Rgz+DO5Fn3+DUzmaOxDJ8nEUCyy7+Ot5P6J0s lzxpbBjQFxse53t1DAYoWD5bH9mMMjVPIP/T4l6WJpO6/wfvwqti+fs5IhYYOKUc S/a6BKZA4g/ntLhb9QWs6Bc07yEvW1z61SCh7gQmZicMNVApx/KO/7jZqDJQNaZt +jY7IEoQnZN83tPiOzjWVpBJPBJqpy2mmfM4kA2luTO2KfDmT46Pf+wHF8b+U8bJ pH9VRViKv9fjLm31 =WlYI -----END PGP SIGNATURE----- Merge tag 'arch-timer-errata' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into clockevents/4.12 arm64 arch timer workaround series, including the base patches that will also go via the arm64 tree. Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>hifive-unleashed-5.1
Daniel Lezcano
commit
6f9c89000c
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@ -54,6 +54,7 @@ stable kernels.
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| ARM | Cortex-A57 | #852523 | N/A |
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| ARM | Cortex-A57 | #834220 | ARM64_ERRATUM_834220 |
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| ARM | Cortex-A72 | #853709 | N/A |
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| ARM | Cortex-A73 | #858921 | ARM64_ERRATUM_858921 |
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| ARM | MMU-500 | #841119,#826419 | N/A |
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| | | | |
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| Cavium | ThunderX ITS | #22375, #24313 | CAVIUM_ERRATUM_22375 |
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@ -25,6 +25,7 @@
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#include <linux/bug.h>
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#include <linux/init.h>
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#include <linux/jump_label.h>
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#include <linux/smp.h>
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#include <linux/types.h>
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#include <clocksource/arm_arch_timer.h>
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@ -37,24 +38,44 @@ extern struct static_key_false arch_timer_read_ool_enabled;
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#define needs_unstable_timer_counter_workaround() false
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#endif
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enum arch_timer_erratum_match_type {
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ate_match_dt,
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ate_match_local_cap_id,
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ate_match_acpi_oem_info,
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};
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struct clock_event_device;
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struct arch_timer_erratum_workaround {
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const char *id; /* Indicate the Erratum ID */
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enum arch_timer_erratum_match_type match_type;
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const void *id;
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const char *desc;
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u32 (*read_cntp_tval_el0)(void);
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u32 (*read_cntv_tval_el0)(void);
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u64 (*read_cntvct_el0)(void);
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int (*set_next_event_phys)(unsigned long, struct clock_event_device *);
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int (*set_next_event_virt)(unsigned long, struct clock_event_device *);
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};
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extern const struct arch_timer_erratum_workaround *timer_unstable_counter_workaround;
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DECLARE_PER_CPU(const struct arch_timer_erratum_workaround *,
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timer_unstable_counter_workaround);
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#define arch_timer_reg_read_stable(reg) \
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({ \
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u64 _val; \
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if (needs_unstable_timer_counter_workaround()) \
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_val = timer_unstable_counter_workaround->read_##reg();\
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else \
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_val = read_sysreg(reg); \
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_val; \
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#define arch_timer_reg_read_stable(reg) \
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({ \
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u64 _val; \
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if (needs_unstable_timer_counter_workaround()) { \
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const struct arch_timer_erratum_workaround *wa; \
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preempt_disable(); \
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wa = __this_cpu_read(timer_unstable_counter_workaround); \
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if (wa && wa->read_##reg) \
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_val = wa->read_##reg(); \
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else \
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_val = read_sysreg(reg); \
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preempt_enable(); \
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} else { \
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_val = read_sysreg(reg); \
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} \
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_val; \
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})
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/*
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@ -37,7 +37,8 @@
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#define ARM64_HAS_NO_FPSIMD 16
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#define ARM64_WORKAROUND_REPEAT_TLBI 17
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#define ARM64_WORKAROUND_QCOM_FALKOR_E1003 18
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#define ARM64_WORKAROUND_858921 19
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#define ARM64_NCAPS 19
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#define ARM64_NCAPS 20
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#endif /* __ASM_CPUCAPS_H */
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@ -80,6 +80,7 @@
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#define ARM_CPU_PART_FOUNDATION 0xD00
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#define ARM_CPU_PART_CORTEX_A57 0xD07
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#define ARM_CPU_PART_CORTEX_A53 0xD03
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#define ARM_CPU_PART_CORTEX_A73 0xD09
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#define APM_CPU_PART_POTENZA 0x000
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@ -92,6 +93,7 @@
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#define MIDR_CORTEX_A53 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A53)
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#define MIDR_CORTEX_A57 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A57)
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#define MIDR_CORTEX_A73 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A73)
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#define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
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#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
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#define MIDR_QCOM_FALKOR_V1 MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, QCOM_CPU_PART_FALKOR_V1)
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@ -175,6 +175,8 @@
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#define ESR_ELx_SYS64_ISS_SYS_CTR_READ (ESR_ELx_SYS64_ISS_SYS_CTR | \
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ESR_ELx_SYS64_ISS_DIR_READ)
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#define ESR_ELx_SYS64_ISS_SYS_CNTVCT (ESR_ELx_SYS64_ISS_SYS_VAL(3, 3, 2, 14, 0) | \
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ESR_ELx_SYS64_ISS_DIR_READ)
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#ifndef __ASSEMBLY__
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#include <asm/types.h>
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@ -53,6 +53,13 @@ static int cpu_enable_trap_ctr_access(void *__unused)
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.midr_range_min = min, \
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.midr_range_max = max
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#define MIDR_ALL_VERSIONS(model) \
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.def_scope = SCOPE_LOCAL_CPU, \
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.matches = is_affected_midr_range, \
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.midr_model = model, \
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.midr_range_min = 0, \
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.midr_range_max = (MIDR_VARIANT_MASK | MIDR_REVISION_MASK)
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const struct arm64_cpu_capabilities arm64_errata[] = {
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#if defined(CONFIG_ARM64_ERRATUM_826319) || \
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defined(CONFIG_ARM64_ERRATUM_827319) || \
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@ -150,6 +157,14 @@ const struct arm64_cpu_capabilities arm64_errata[] = {
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MIDR_CPU_VAR_REV(0, 0),
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MIDR_CPU_VAR_REV(0, 0)),
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},
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#endif
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#ifdef CONFIG_ARM64_ERRATUM_858921
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{
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/* Cortex-A73 all versions */
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.desc = "ARM erratum 858921",
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.capability = ARM64_WORKAROUND_858921,
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A73),
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},
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#endif
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{
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}
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@ -1090,20 +1090,29 @@ static void __init setup_feature_capabilities(void)
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* Check if the current CPU has a given feature capability.
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* Should be called from non-preemptible context.
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*/
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bool this_cpu_has_cap(unsigned int cap)
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static bool __this_cpu_has_cap(const struct arm64_cpu_capabilities *cap_array,
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unsigned int cap)
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{
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const struct arm64_cpu_capabilities *caps;
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if (WARN_ON(preemptible()))
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return false;
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for (caps = arm64_features; caps->desc; caps++)
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for (caps = cap_array; caps->desc; caps++)
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if (caps->capability == cap && caps->matches)
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return caps->matches(caps, SCOPE_LOCAL_CPU);
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return false;
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}
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extern const struct arm64_cpu_capabilities arm64_errata[];
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bool this_cpu_has_cap(unsigned int cap)
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{
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return (__this_cpu_has_cap(arm64_features, cap) ||
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__this_cpu_has_cap(arm64_errata, cap));
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}
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void __init setup_cpu_features(void)
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{
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u32 cwg;
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@ -505,6 +505,14 @@ static void ctr_read_handler(unsigned int esr, struct pt_regs *regs)
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regs->pc += 4;
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}
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static void cntvct_read_handler(unsigned int esr, struct pt_regs *regs)
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{
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int rt = (esr & ESR_ELx_SYS64_ISS_RT_MASK) >> ESR_ELx_SYS64_ISS_RT_SHIFT;
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pt_regs_write_reg(regs, rt, arch_counter_get_cntvct());
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regs->pc += 4;
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}
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struct sys64_hook {
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unsigned int esr_mask;
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unsigned int esr_val;
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@ -523,6 +531,12 @@ static struct sys64_hook sys64_hooks[] = {
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.esr_val = ESR_ELx_SYS64_ISS_SYS_CTR_READ,
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.handler = ctr_read_handler,
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},
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{
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/* Trap read access to CNTVCT_EL0 */
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.esr_mask = ESR_ELx_SYS64_ISS_SYS_OP_MASK,
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.esr_val = ESR_ELx_SYS64_ISS_SYS_CNTVCT,
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.handler = cntvct_read_handler,
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},
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{},
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};
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@ -368,6 +368,17 @@ config HISILICON_ERRATUM_161010101
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161010101. The workaround will be active if the hisilicon,erratum-161010101
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property is found in the timer node.
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config ARM64_ERRATUM_858921
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bool "Workaround for Cortex-A73 erratum 858921"
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default y
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select ARM_ARCH_TIMER_OOL_WORKAROUND
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depends on ARM_ARCH_TIMER && ARM64
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help
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This option enables a workaround applicable to Cortex-A73
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(all versions), whose counter may return incorrect values.
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The workaround will be dynamically enabled when an affected
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core is detected.
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config ARM_GLOBAL_TIMER
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bool "Support for the ARM global timer" if COMPILE_TEST
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select CLKSRC_OF if OF
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@ -83,6 +83,7 @@ static enum ppi_nr arch_timer_uses_ppi = VIRT_PPI;
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static bool arch_timer_c3stop;
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static bool arch_timer_mem_use_virtual;
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static bool arch_counter_suspend_stop;
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static bool vdso_default = true;
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static bool evtstrm_enable = IS_ENABLED(CONFIG_ARM_ARCH_TIMER_EVTSTREAM);
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@ -96,6 +97,105 @@ early_param("clocksource.arm_arch_timer.evtstrm", early_evtstrm_cfg);
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* Architected system timer support.
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*/
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static __always_inline
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void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val,
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struct clock_event_device *clk)
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{
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if (access == ARCH_TIMER_MEM_PHYS_ACCESS) {
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struct arch_timer *timer = to_arch_timer(clk);
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switch (reg) {
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case ARCH_TIMER_REG_CTRL:
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writel_relaxed(val, timer->base + CNTP_CTL);
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break;
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case ARCH_TIMER_REG_TVAL:
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writel_relaxed(val, timer->base + CNTP_TVAL);
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break;
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}
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} else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) {
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struct arch_timer *timer = to_arch_timer(clk);
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switch (reg) {
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case ARCH_TIMER_REG_CTRL:
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writel_relaxed(val, timer->base + CNTV_CTL);
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break;
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case ARCH_TIMER_REG_TVAL:
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writel_relaxed(val, timer->base + CNTV_TVAL);
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break;
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}
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} else {
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arch_timer_reg_write_cp15(access, reg, val);
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}
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}
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static __always_inline
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u32 arch_timer_reg_read(int access, enum arch_timer_reg reg,
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struct clock_event_device *clk)
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{
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u32 val;
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if (access == ARCH_TIMER_MEM_PHYS_ACCESS) {
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struct arch_timer *timer = to_arch_timer(clk);
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switch (reg) {
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case ARCH_TIMER_REG_CTRL:
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val = readl_relaxed(timer->base + CNTP_CTL);
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break;
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case ARCH_TIMER_REG_TVAL:
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val = readl_relaxed(timer->base + CNTP_TVAL);
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break;
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}
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} else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) {
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struct arch_timer *timer = to_arch_timer(clk);
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switch (reg) {
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case ARCH_TIMER_REG_CTRL:
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val = readl_relaxed(timer->base + CNTV_CTL);
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break;
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case ARCH_TIMER_REG_TVAL:
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val = readl_relaxed(timer->base + CNTV_TVAL);
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break;
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}
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} else {
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val = arch_timer_reg_read_cp15(access, reg);
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}
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return val;
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}
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/*
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* Default to cp15 based access because arm64 uses this function for
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* sched_clock() before DT is probed and the cp15 method is guaranteed
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* to exist on arm64. arm doesn't use this before DT is probed so even
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* if we don't have the cp15 accessors we won't have a problem.
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*/
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u64 (*arch_timer_read_counter)(void) = arch_counter_get_cntvct;
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static u64 arch_counter_read(struct clocksource *cs)
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{
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return arch_timer_read_counter();
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}
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static u64 arch_counter_read_cc(const struct cyclecounter *cc)
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{
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return arch_timer_read_counter();
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}
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static struct clocksource clocksource_counter = {
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.name = "arch_sys_counter",
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.rating = 400,
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.read = arch_counter_read,
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.mask = CLOCKSOURCE_MASK(56),
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.flags = CLOCK_SOURCE_IS_CONTINUOUS,
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};
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static struct cyclecounter cyclecounter __ro_after_init = {
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.read = arch_counter_read_cc,
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.mask = CLOCKSOURCE_MASK(56),
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};
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struct ate_acpi_oem_info {
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char oem_id[ACPI_OEM_ID_SIZE + 1];
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char oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1];
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u32 oem_revision;
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};
|
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|
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#ifdef CONFIG_FSL_ERRATUM_A008585
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/*
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* The number of retries is an arbitrary value well beyond the highest number
|
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|
|
@ -170,97 +270,289 @@ static u64 notrace hisi_161010101_read_cntvct_el0(void)
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{
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return __hisi_161010101_read_reg(cntvct_el0);
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}
|
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|
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static struct ate_acpi_oem_info hisi_161010101_oem_info[] = {
|
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/*
|
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* Note that trailing spaces are required to properly match
|
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* the OEM table information.
|
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*/
|
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{
|
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.oem_id = "HISI ",
|
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.oem_table_id = "HIP05 ",
|
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.oem_revision = 0,
|
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},
|
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{
|
||||
.oem_id = "HISI ",
|
||||
.oem_table_id = "HIP06 ",
|
||||
.oem_revision = 0,
|
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},
|
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{
|
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.oem_id = "HISI ",
|
||||
.oem_table_id = "HIP07 ",
|
||||
.oem_revision = 0,
|
||||
},
|
||||
{ /* Sentinel indicating the end of the OEM array */ },
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARM64_ERRATUM_858921
|
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static u64 notrace arm64_858921_read_cntvct_el0(void)
|
||||
{
|
||||
u64 old, new;
|
||||
|
||||
old = read_sysreg(cntvct_el0);
|
||||
new = read_sysreg(cntvct_el0);
|
||||
return (((old ^ new) >> 32) & 1) ? old : new;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND
|
||||
const struct arch_timer_erratum_workaround *timer_unstable_counter_workaround = NULL;
|
||||
DEFINE_PER_CPU(const struct arch_timer_erratum_workaround *,
|
||||
timer_unstable_counter_workaround);
|
||||
EXPORT_SYMBOL_GPL(timer_unstable_counter_workaround);
|
||||
|
||||
DEFINE_STATIC_KEY_FALSE(arch_timer_read_ool_enabled);
|
||||
EXPORT_SYMBOL_GPL(arch_timer_read_ool_enabled);
|
||||
|
||||
static void erratum_set_next_event_tval_generic(const int access, unsigned long evt,
|
||||
struct clock_event_device *clk)
|
||||
{
|
||||
unsigned long ctrl;
|
||||
u64 cval = evt + arch_counter_get_cntvct();
|
||||
|
||||
ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
|
||||
ctrl |= ARCH_TIMER_CTRL_ENABLE;
|
||||
ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
|
||||
|
||||
if (access == ARCH_TIMER_PHYS_ACCESS)
|
||||
write_sysreg(cval, cntp_cval_el0);
|
||||
else
|
||||
write_sysreg(cval, cntv_cval_el0);
|
||||
|
||||
arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
|
||||
}
|
||||
|
||||
static int erratum_set_next_event_tval_virt(unsigned long evt,
|
||||
struct clock_event_device *clk)
|
||||
{
|
||||
erratum_set_next_event_tval_generic(ARCH_TIMER_VIRT_ACCESS, evt, clk);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int erratum_set_next_event_tval_phys(unsigned long evt,
|
||||
struct clock_event_device *clk)
|
||||
{
|
||||
erratum_set_next_event_tval_generic(ARCH_TIMER_PHYS_ACCESS, evt, clk);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct arch_timer_erratum_workaround ool_workarounds[] = {
|
||||
#ifdef CONFIG_FSL_ERRATUM_A008585
|
||||
{
|
||||
.match_type = ate_match_dt,
|
||||
.id = "fsl,erratum-a008585",
|
||||
.desc = "Freescale erratum a005858",
|
||||
.read_cntp_tval_el0 = fsl_a008585_read_cntp_tval_el0,
|
||||
.read_cntv_tval_el0 = fsl_a008585_read_cntv_tval_el0,
|
||||
.read_cntvct_el0 = fsl_a008585_read_cntvct_el0,
|
||||
.set_next_event_phys = erratum_set_next_event_tval_phys,
|
||||
.set_next_event_virt = erratum_set_next_event_tval_virt,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_HISILICON_ERRATUM_161010101
|
||||
{
|
||||
.match_type = ate_match_dt,
|
||||
.id = "hisilicon,erratum-161010101",
|
||||
.desc = "HiSilicon erratum 161010101",
|
||||
.read_cntp_tval_el0 = hisi_161010101_read_cntp_tval_el0,
|
||||
.read_cntv_tval_el0 = hisi_161010101_read_cntv_tval_el0,
|
||||
.read_cntvct_el0 = hisi_161010101_read_cntvct_el0,
|
||||
.set_next_event_phys = erratum_set_next_event_tval_phys,
|
||||
.set_next_event_virt = erratum_set_next_event_tval_virt,
|
||||
},
|
||||
{
|
||||
.match_type = ate_match_acpi_oem_info,
|
||||
.id = hisi_161010101_oem_info,
|
||||
.desc = "HiSilicon erratum 161010101",
|
||||
.read_cntp_tval_el0 = hisi_161010101_read_cntp_tval_el0,
|
||||
.read_cntv_tval_el0 = hisi_161010101_read_cntv_tval_el0,
|
||||
.read_cntvct_el0 = hisi_161010101_read_cntvct_el0,
|
||||
.set_next_event_phys = erratum_set_next_event_tval_phys,
|
||||
.set_next_event_virt = erratum_set_next_event_tval_virt,
|
||||
},
|
||||
#endif
|
||||
#ifdef CONFIG_ARM64_ERRATUM_858921
|
||||
{
|
||||
.match_type = ate_match_local_cap_id,
|
||||
.id = (void *)ARM64_WORKAROUND_858921,
|
||||
.desc = "ARM erratum 858921",
|
||||
.read_cntvct_el0 = arm64_858921_read_cntvct_el0,
|
||||
},
|
||||
#endif
|
||||
};
|
||||
|
||||
typedef bool (*ate_match_fn_t)(const struct arch_timer_erratum_workaround *,
|
||||
const void *);
|
||||
|
||||
static
|
||||
bool arch_timer_check_dt_erratum(const struct arch_timer_erratum_workaround *wa,
|
||||
const void *arg)
|
||||
{
|
||||
const struct device_node *np = arg;
|
||||
|
||||
return of_property_read_bool(np, wa->id);
|
||||
}
|
||||
|
||||
static
|
||||
bool arch_timer_check_local_cap_erratum(const struct arch_timer_erratum_workaround *wa,
|
||||
const void *arg)
|
||||
{
|
||||
return this_cpu_has_cap((uintptr_t)wa->id);
|
||||
}
|
||||
|
||||
|
||||
static
|
||||
bool arch_timer_check_acpi_oem_erratum(const struct arch_timer_erratum_workaround *wa,
|
||||
const void *arg)
|
||||
{
|
||||
static const struct ate_acpi_oem_info empty_oem_info = {};
|
||||
const struct ate_acpi_oem_info *info = wa->id;
|
||||
const struct acpi_table_header *table = arg;
|
||||
|
||||
/* Iterate over the ACPI OEM info array, looking for a match */
|
||||
while (memcmp(info, &empty_oem_info, sizeof(*info))) {
|
||||
if (!memcmp(info->oem_id, table->oem_id, ACPI_OEM_ID_SIZE) &&
|
||||
!memcmp(info->oem_table_id, table->oem_table_id, ACPI_OEM_TABLE_ID_SIZE) &&
|
||||
info->oem_revision == table->oem_revision)
|
||||
return true;
|
||||
|
||||
info++;
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
|
||||
static const struct arch_timer_erratum_workaround *
|
||||
arch_timer_iterate_errata(enum arch_timer_erratum_match_type type,
|
||||
ate_match_fn_t match_fn,
|
||||
void *arg)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(ool_workarounds); i++) {
|
||||
if (ool_workarounds[i].match_type != type)
|
||||
continue;
|
||||
|
||||
if (match_fn(&ool_workarounds[i], arg))
|
||||
return &ool_workarounds[i];
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static
|
||||
void arch_timer_enable_workaround(const struct arch_timer_erratum_workaround *wa,
|
||||
bool local)
|
||||
{
|
||||
int i;
|
||||
|
||||
if (local) {
|
||||
__this_cpu_write(timer_unstable_counter_workaround, wa);
|
||||
} else {
|
||||
for_each_possible_cpu(i)
|
||||
per_cpu(timer_unstable_counter_workaround, i) = wa;
|
||||
}
|
||||
|
||||
static_branch_enable(&arch_timer_read_ool_enabled);
|
||||
|
||||
/*
|
||||
* Don't use the vdso fastpath if errata require using the
|
||||
* out-of-line counter accessor. We may change our mind pretty
|
||||
* late in the game (with a per-CPU erratum, for example), so
|
||||
* change both the default value and the vdso itself.
|
||||
*/
|
||||
if (wa->read_cntvct_el0) {
|
||||
clocksource_counter.archdata.vdso_direct = false;
|
||||
vdso_default = false;
|
||||
}
|
||||
}
|
||||
|
||||
static void arch_timer_check_ool_workaround(enum arch_timer_erratum_match_type type,
|
||||
void *arg)
|
||||
{
|
||||
const struct arch_timer_erratum_workaround *wa;
|
||||
ate_match_fn_t match_fn = NULL;
|
||||
bool local = false;
|
||||
|
||||
switch (type) {
|
||||
case ate_match_dt:
|
||||
match_fn = arch_timer_check_dt_erratum;
|
||||
break;
|
||||
case ate_match_local_cap_id:
|
||||
match_fn = arch_timer_check_local_cap_erratum;
|
||||
local = true;
|
||||
break;
|
||||
case ate_match_acpi_oem_info:
|
||||
match_fn = arch_timer_check_acpi_oem_erratum;
|
||||
break;
|
||||
default:
|
||||
WARN_ON(1);
|
||||
return;
|
||||
}
|
||||
|
||||
wa = arch_timer_iterate_errata(type, match_fn, arg);
|
||||
if (!wa)
|
||||
return;
|
||||
|
||||
if (needs_unstable_timer_counter_workaround()) {
|
||||
const struct arch_timer_erratum_workaround *__wa;
|
||||
__wa = __this_cpu_read(timer_unstable_counter_workaround);
|
||||
if (__wa && wa != __wa)
|
||||
pr_warn("Can't enable workaround for %s (clashes with %s\n)",
|
||||
wa->desc, __wa->desc);
|
||||
|
||||
if (__wa)
|
||||
return;
|
||||
}
|
||||
|
||||
arch_timer_enable_workaround(wa, local);
|
||||
pr_info("Enabling %s workaround for %s\n",
|
||||
local ? "local" : "global", wa->desc);
|
||||
}
|
||||
|
||||
#define erratum_handler(fn, r, ...) \
|
||||
({ \
|
||||
bool __val; \
|
||||
if (needs_unstable_timer_counter_workaround()) { \
|
||||
const struct arch_timer_erratum_workaround *__wa; \
|
||||
__wa = __this_cpu_read(timer_unstable_counter_workaround); \
|
||||
if (__wa && __wa->fn) { \
|
||||
r = __wa->fn(__VA_ARGS__); \
|
||||
__val = true; \
|
||||
} else { \
|
||||
__val = false; \
|
||||
} \
|
||||
} else { \
|
||||
__val = false; \
|
||||
} \
|
||||
__val; \
|
||||
})
|
||||
|
||||
static bool arch_timer_this_cpu_has_cntvct_wa(void)
|
||||
{
|
||||
const struct arch_timer_erratum_workaround *wa;
|
||||
|
||||
wa = __this_cpu_read(timer_unstable_counter_workaround);
|
||||
return wa && wa->read_cntvct_el0;
|
||||
}
|
||||
#else
|
||||
#define arch_timer_check_ool_workaround(t,a) do { } while(0)
|
||||
#define erratum_set_next_event_tval_virt(...) ({BUG(); 0;})
|
||||
#define erratum_set_next_event_tval_phys(...) ({BUG(); 0;})
|
||||
#define erratum_handler(fn, r, ...) ({false;})
|
||||
#define arch_timer_this_cpu_has_cntvct_wa() ({false;})
|
||||
#endif /* CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND */
|
||||
|
||||
static __always_inline
|
||||
void arch_timer_reg_write(int access, enum arch_timer_reg reg, u32 val,
|
||||
struct clock_event_device *clk)
|
||||
{
|
||||
if (access == ARCH_TIMER_MEM_PHYS_ACCESS) {
|
||||
struct arch_timer *timer = to_arch_timer(clk);
|
||||
switch (reg) {
|
||||
case ARCH_TIMER_REG_CTRL:
|
||||
writel_relaxed(val, timer->base + CNTP_CTL);
|
||||
break;
|
||||
case ARCH_TIMER_REG_TVAL:
|
||||
writel_relaxed(val, timer->base + CNTP_TVAL);
|
||||
break;
|
||||
}
|
||||
} else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) {
|
||||
struct arch_timer *timer = to_arch_timer(clk);
|
||||
switch (reg) {
|
||||
case ARCH_TIMER_REG_CTRL:
|
||||
writel_relaxed(val, timer->base + CNTV_CTL);
|
||||
break;
|
||||
case ARCH_TIMER_REG_TVAL:
|
||||
writel_relaxed(val, timer->base + CNTV_TVAL);
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
arch_timer_reg_write_cp15(access, reg, val);
|
||||
}
|
||||
}
|
||||
|
||||
static __always_inline
|
||||
u32 arch_timer_reg_read(int access, enum arch_timer_reg reg,
|
||||
struct clock_event_device *clk)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
if (access == ARCH_TIMER_MEM_PHYS_ACCESS) {
|
||||
struct arch_timer *timer = to_arch_timer(clk);
|
||||
switch (reg) {
|
||||
case ARCH_TIMER_REG_CTRL:
|
||||
val = readl_relaxed(timer->base + CNTP_CTL);
|
||||
break;
|
||||
case ARCH_TIMER_REG_TVAL:
|
||||
val = readl_relaxed(timer->base + CNTP_TVAL);
|
||||
break;
|
||||
}
|
||||
} else if (access == ARCH_TIMER_MEM_VIRT_ACCESS) {
|
||||
struct arch_timer *timer = to_arch_timer(clk);
|
||||
switch (reg) {
|
||||
case ARCH_TIMER_REG_CTRL:
|
||||
val = readl_relaxed(timer->base + CNTV_CTL);
|
||||
break;
|
||||
case ARCH_TIMER_REG_TVAL:
|
||||
val = readl_relaxed(timer->base + CNTV_TVAL);
|
||||
break;
|
||||
}
|
||||
} else {
|
||||
val = arch_timer_reg_read_cp15(access, reg);
|
||||
}
|
||||
|
||||
return val;
|
||||
}
|
||||
|
||||
static __always_inline irqreturn_t timer_handler(const int access,
|
||||
struct clock_event_device *evt)
|
||||
{
|
||||
|
|
@ -348,43 +640,14 @@ static __always_inline void set_next_event(const int access, unsigned long evt,
|
|||
arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND
|
||||
static __always_inline void erratum_set_next_event_generic(const int access,
|
||||
unsigned long evt, struct clock_event_device *clk)
|
||||
{
|
||||
unsigned long ctrl;
|
||||
u64 cval = evt + arch_counter_get_cntvct();
|
||||
|
||||
ctrl = arch_timer_reg_read(access, ARCH_TIMER_REG_CTRL, clk);
|
||||
ctrl |= ARCH_TIMER_CTRL_ENABLE;
|
||||
ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
|
||||
|
||||
if (access == ARCH_TIMER_PHYS_ACCESS)
|
||||
write_sysreg(cval, cntp_cval_el0);
|
||||
else if (access == ARCH_TIMER_VIRT_ACCESS)
|
||||
write_sysreg(cval, cntv_cval_el0);
|
||||
|
||||
arch_timer_reg_write(access, ARCH_TIMER_REG_CTRL, ctrl, clk);
|
||||
}
|
||||
|
||||
static int erratum_set_next_event_virt(unsigned long evt,
|
||||
struct clock_event_device *clk)
|
||||
{
|
||||
erratum_set_next_event_generic(ARCH_TIMER_VIRT_ACCESS, evt, clk);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int erratum_set_next_event_phys(unsigned long evt,
|
||||
struct clock_event_device *clk)
|
||||
{
|
||||
erratum_set_next_event_generic(ARCH_TIMER_PHYS_ACCESS, evt, clk);
|
||||
return 0;
|
||||
}
|
||||
#endif /* CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND */
|
||||
|
||||
static int arch_timer_set_next_event_virt(unsigned long evt,
|
||||
struct clock_event_device *clk)
|
||||
{
|
||||
int ret;
|
||||
|
||||
if (erratum_handler(set_next_event_virt, ret, evt, clk))
|
||||
return ret;
|
||||
|
||||
set_next_event(ARCH_TIMER_VIRT_ACCESS, evt, clk);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -392,6 +655,11 @@ static int arch_timer_set_next_event_virt(unsigned long evt,
|
|||
static int arch_timer_set_next_event_phys(unsigned long evt,
|
||||
struct clock_event_device *clk)
|
||||
{
|
||||
int ret;
|
||||
|
||||
if (erratum_handler(set_next_event_phys, ret, evt, clk))
|
||||
return ret;
|
||||
|
||||
set_next_event(ARCH_TIMER_PHYS_ACCESS, evt, clk);
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -410,19 +678,6 @@ static int arch_timer_set_next_event_phys_mem(unsigned long evt,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static void erratum_workaround_set_sne(struct clock_event_device *clk)
|
||||
{
|
||||
#ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND
|
||||
if (!static_branch_unlikely(&arch_timer_read_ool_enabled))
|
||||
return;
|
||||
|
||||
if (arch_timer_uses_ppi == VIRT_PPI)
|
||||
clk->set_next_event = erratum_set_next_event_virt;
|
||||
else
|
||||
clk->set_next_event = erratum_set_next_event_phys;
|
||||
#endif
|
||||
}
|
||||
|
||||
static void __arch_timer_setup(unsigned type,
|
||||
struct clock_event_device *clk)
|
||||
{
|
||||
|
|
@ -452,7 +707,7 @@ static void __arch_timer_setup(unsigned type,
|
|||
BUG();
|
||||
}
|
||||
|
||||
erratum_workaround_set_sne(clk);
|
||||
arch_timer_check_ool_workaround(ate_match_local_cap_id, NULL);
|
||||
} else {
|
||||
clk->features |= CLOCK_EVT_FEAT_DYNIRQ;
|
||||
clk->name = "arch_mem_timer";
|
||||
|
|
@ -508,15 +763,23 @@ static void arch_counter_set_user_access(void)
|
|||
{
|
||||
u32 cntkctl = arch_timer_get_cntkctl();
|
||||
|
||||
/* Disable user access to the timers and the physical counter */
|
||||
/* Disable user access to the timers and both counters */
|
||||
/* Also disable virtual event stream */
|
||||
cntkctl &= ~(ARCH_TIMER_USR_PT_ACCESS_EN
|
||||
| ARCH_TIMER_USR_VT_ACCESS_EN
|
||||
| ARCH_TIMER_USR_VCT_ACCESS_EN
|
||||
| ARCH_TIMER_VIRT_EVT_EN
|
||||
| ARCH_TIMER_USR_PCT_ACCESS_EN);
|
||||
|
||||
/* Enable user access to the virtual counter */
|
||||
cntkctl |= ARCH_TIMER_USR_VCT_ACCESS_EN;
|
||||
/*
|
||||
* Enable user access to the virtual counter if it doesn't
|
||||
* need to be workaround. The vdso may have been already
|
||||
* disabled though.
|
||||
*/
|
||||
if (arch_timer_this_cpu_has_cntvct_wa())
|
||||
pr_info("CPU%d: Trapping CNTVCT access\n", smp_processor_id());
|
||||
else
|
||||
cntkctl |= ARCH_TIMER_USR_VCT_ACCESS_EN;
|
||||
|
||||
arch_timer_set_cntkctl(cntkctl);
|
||||
}
|
||||
|
|
@ -621,37 +884,6 @@ static u64 arch_counter_get_cntvct_mem(void)
|
|||
return ((u64) vct_hi << 32) | vct_lo;
|
||||
}
|
||||
|
||||
/*
|
||||
* Default to cp15 based access because arm64 uses this function for
|
||||
* sched_clock() before DT is probed and the cp15 method is guaranteed
|
||||
* to exist on arm64. arm doesn't use this before DT is probed so even
|
||||
* if we don't have the cp15 accessors we won't have a problem.
|
||||
*/
|
||||
u64 (*arch_timer_read_counter)(void) = arch_counter_get_cntvct;
|
||||
|
||||
static u64 arch_counter_read(struct clocksource *cs)
|
||||
{
|
||||
return arch_timer_read_counter();
|
||||
}
|
||||
|
||||
static u64 arch_counter_read_cc(const struct cyclecounter *cc)
|
||||
{
|
||||
return arch_timer_read_counter();
|
||||
}
|
||||
|
||||
static struct clocksource clocksource_counter = {
|
||||
.name = "arch_sys_counter",
|
||||
.rating = 400,
|
||||
.read = arch_counter_read,
|
||||
.mask = CLOCKSOURCE_MASK(56),
|
||||
.flags = CLOCK_SOURCE_IS_CONTINUOUS,
|
||||
};
|
||||
|
||||
static struct cyclecounter cyclecounter __ro_after_init = {
|
||||
.read = arch_counter_read_cc,
|
||||
.mask = CLOCKSOURCE_MASK(56),
|
||||
};
|
||||
|
||||
static struct arch_timer_kvm_info arch_timer_kvm_info;
|
||||
|
||||
struct arch_timer_kvm_info *arch_timer_get_kvm_info(void)
|
||||
|
|
@ -670,16 +902,7 @@ static void __init arch_counter_register(unsigned type)
|
|||
else
|
||||
arch_timer_read_counter = arch_counter_get_cntpct;
|
||||
|
||||
clocksource_counter.archdata.vdso_direct = true;
|
||||
|
||||
#ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND
|
||||
/*
|
||||
* Don't use the vdso fastpath if errata require using
|
||||
* the out-of-line counter accessor.
|
||||
*/
|
||||
if (static_branch_unlikely(&arch_timer_read_ool_enabled))
|
||||
clocksource_counter.archdata.vdso_direct = false;
|
||||
#endif
|
||||
clocksource_counter.archdata.vdso_direct = vdso_default;
|
||||
} else {
|
||||
arch_timer_read_counter = arch_counter_get_cntvct_mem;
|
||||
}
|
||||
|
|
@ -718,14 +941,14 @@ static int arch_timer_dying_cpu(unsigned int cpu)
|
|||
}
|
||||
|
||||
#ifdef CONFIG_CPU_PM
|
||||
static unsigned int saved_cntkctl;
|
||||
static DEFINE_PER_CPU(unsigned long, saved_cntkctl);
|
||||
static int arch_timer_cpu_pm_notify(struct notifier_block *self,
|
||||
unsigned long action, void *hcpu)
|
||||
{
|
||||
if (action == CPU_PM_ENTER)
|
||||
saved_cntkctl = arch_timer_get_cntkctl();
|
||||
__this_cpu_write(saved_cntkctl, arch_timer_get_cntkctl());
|
||||
else if (action == CPU_PM_ENTER_FAILED || action == CPU_PM_EXIT)
|
||||
arch_timer_set_cntkctl(saved_cntkctl);
|
||||
arch_timer_set_cntkctl(__this_cpu_read(saved_cntkctl));
|
||||
return NOTIFY_OK;
|
||||
}
|
||||
|
||||
|
|
@ -960,17 +1183,8 @@ static int __init arch_timer_of_init(struct device_node *np)
|
|||
|
||||
arch_timer_c3stop = !of_property_read_bool(np, "always-on");
|
||||
|
||||
#ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND
|
||||
for (i = 0; i < ARRAY_SIZE(ool_workarounds); i++) {
|
||||
if (of_property_read_bool(np, ool_workarounds[i].id)) {
|
||||
timer_unstable_counter_workaround = &ool_workarounds[i];
|
||||
static_branch_enable(&arch_timer_read_ool_enabled);
|
||||
pr_info("arch_timer: Enabling workaround for %s\n",
|
||||
timer_unstable_counter_workaround->id);
|
||||
break;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
/* Check for globally applicable workarounds */
|
||||
arch_timer_check_ool_workaround(ate_match_dt, np);
|
||||
|
||||
/*
|
||||
* If we cannot rely on firmware initializing the timer registers then
|
||||
|
|
@ -1127,6 +1341,9 @@ static int __init arch_timer_acpi_init(struct acpi_table_header *table)
|
|||
/* Always-on capability */
|
||||
arch_timer_c3stop = !(gtdt->non_secure_el1_flags & ACPI_GTDT_ALWAYS_ON);
|
||||
|
||||
/* Check for globally applicable workarounds */
|
||||
arch_timer_check_ool_workaround(ate_match_acpi_oem_info, table);
|
||||
|
||||
arch_timer_init();
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue