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arm64: dts: imx8qxp: enable enet1 port 

Currently enet cannot work due to the wrong clock tree and
incorrect IO voltage, correct them.

Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
5.4-rM2-2.2.x-imx-squashed
Fugang Duan 2019-06-05 18:36:02 +08:00 committed by Dong Aisheng
parent 09c09cbf91
commit 6fac62a282
3 changed files with 40 additions and 4 deletions
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14
arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
View File

@ -107,9 +107,12 @@ conn_subsys: bus@5b000000 {
<GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&conn_lpcg IMX_CONN_LPCG_ENET0_IPG_CLK>,
<&conn_lpcg IMX_CONN_LPCG_ENET0_AHB_CLK>,
<&conn_lpcg IMX_CONN_LPCG_ENET0_TX_CLK>,
<&conn_lpcg IMX_CONN_LPCG_ENET0_ROOT_CLK>;
<&conn_lpcg IMX_CONN_LPCG_ENET0_RGMII_TXC_CLK>,
<&conn_lpcg IMX_CONN_LPCG_ENET0_TIMER_CLK>;
clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
assigned-clocks = <&clk IMX_CONN_ENET0_ROOT_CLK>,
<&clk IMX_CONN_ENET0_REF_DIV>;
assigned-clock-rates = <250000000>, <125000000>;
fsl,num-tx-queues=<3>;
fsl,num-rx-queues=<3>;
power-domains = <&pd IMX_SC_R_ENET_0>;
@ -125,9 +128,12 @@ conn_subsys: bus@5b000000 {
<GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&conn_lpcg IMX_CONN_LPCG_ENET1_IPG_CLK>,
<&conn_lpcg IMX_CONN_LPCG_ENET1_AHB_CLK>,
<&conn_lpcg IMX_CONN_LPCG_ENET1_TX_CLK>,
<&conn_lpcg IMX_CONN_LPCG_ENET1_ROOT_CLK>;
<&conn_lpcg IMX_CONN_LPCG_ENET1_RGMII_TXC_CLK>,
<&conn_lpcg IMX_CONN_LPCG_ENET1_TIMER_CLK>;
clock-names = "ipg", "ahb", "enet_clk_ref", "ptp";
assigned-clocks = <&clk IMX_CONN_ENET1_ROOT_CLK>,
<&clk IMX_CONN_ENET1_REF_DIV>;
assigned-clock-rates = <250000000>, <125000000>;
fsl,num-tx-queues=<3>;
fsl,num-rx-queues=<3>;
power-domains = <&pd IMX_SC_R_ENET_1>;

6
arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
View File

@ -447,11 +447,15 @@
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
at803x,eee-disabled;
at803x,vddio-1p8v;
};
ethphy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
at803x,eee-disabled;
at803x,vddio-1p8v;
};
};
};
@ -765,6 +769,8 @@
pinctrl_fec1: fec1grp {
fsl,pins = <
IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0
IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0
IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020
IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020
IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020

24
include/dt-bindings/pinctrl/pads-imx8qxp.h
View File

@ -748,4 +748,28 @@
#define IMX8QXP_QSPI0B_SS1_B_LSIO_KPP0_ROW3 IMX8QXP_QSPI0B_SS1_B 2
#define IMX8QXP_QSPI0B_SS1_B_LSIO_GPIO3_IO24 IMX8QXP_QSPI0B_SS1_B 4
/*!
* @name Fake Pad Mux Definitions
* format: name padid 0
*/
/*@{*/
#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_PCIESEP_PAD IMX8QXP_COMP_CTL_GPIO_1V8_3V3_PCIESEP 0
#define IMX8QXP_COMP_CTL_GPIO_3V3_USB3IO_PAD IMX8QXP_COMP_CTL_GPIO_3V3_USB3IO 0
#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_SD1FIX0_PAD IMX8QXP_COMP_CTL_GPIO_1V8_3V3_SD1FIX0 0
#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_SD1FIX1_PAD IMX8QXP_COMP_CTL_GPIO_1V8_3V3_SD1FIX1 0
#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_VSELSEP_PAD IMX8QXP_COMP_CTL_GPIO_1V8_3V3_VSELSEP 0
#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_VSEL3_PAD IMX8QXP_COMP_CTL_GPIO_1V8_3V3_VSEL3 0
#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 0
#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD IMX8QXP_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1 0
#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIOCT_PAD IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIOCT 0
#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHB 0
#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHK_PAD IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHK 0
#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHT_PAD IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHT 0
#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIOLH_PAD IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIOLH 0
#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO_PAD IMX8QXP_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO 0
#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHD_PAD IMX8QXP_COMP_CTL_GPIO_1V8_3V3_GPIORHD 0
#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_QSPI0A_PAD IMX8QXP_COMP_CTL_GPIO_1V8_3V3_QSPI0A 0
#define IMX8QXP_COMP_CTL_GPIO_1V8_3V3_QSPI0B_PAD IMX8QXP_COMP_CTL_GPIO_1V8_3V3_QSPI0B 0
/*@}*/
#endif /* _IMX8QXP_PADS_H */