drm/i915: Set SSC frequency for 8xx chips correctly
All 8xx class chips have the 66/48 split, not just 855. Signed-off-by: Ma Ling <ling.ma@intel.com> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Eric Anholt <eric@anholt.net>
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@ -195,10 +195,12 @@ parse_general_features(struct drm_i915_private *dev_priv,
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dev_priv->lvds_use_ssc = general->enable_ssc;
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if (dev_priv->lvds_use_ssc) {
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if (IS_I855(dev_priv->dev))
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dev_priv->lvds_ssc_freq = general->ssc_freq ? 66 : 48;
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else
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dev_priv->lvds_ssc_freq = general->ssc_freq ? 100 : 96;
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if (IS_I85X(dev_priv->dev))
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dev_priv->lvds_ssc_freq =
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general->ssc_freq ? 66 : 48;
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else
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dev_priv->lvds_ssc_freq =
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general->ssc_freq ? 100 : 96;
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}
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}
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}
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